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公开(公告)号：US09646713B2
公开(公告)日：2017-05-09
申请号：US15140023
申请日：2016-04-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C17/18
CPC classification number: G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
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Patent Agency Ranking
公开(公告)号：US09754681B2
公开(公告)日：2017-09-05
申请号：US15446909
申请日：2017-03-01
Applicant: STMicroelectronics S.r.l.
CPC classification number: G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
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公开(公告)号：US10547171B2
公开(公告)日：2020-01-28
申请号：US15596465
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Bruno Mirabella , Francesco Pulvirenti , Salvatore Pappalardo
IPC: H02H9/02 , H02H7/00 , H03K17/082
Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
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公开(公告)号：US20170178744A1
公开(公告)日：2017-06-22
申请号：US15446909
申请日：2017-03-01
Applicant: STMicroelectronics S.r.l.
CPC classification number: G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
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公开(公告)号：US20170011808A1
公开(公告)日：2017-01-12
申请号：US15140023
申请日：2016-04-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C17/18
CPC classification number: G11C17/18 , G11C11/4125 , G11C17/16 , H03K3/02335 , H03K19/00338 , H03K19/17764
Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
Abstract translation: 辐射硬化的存储单元包括被配置为冗余地存储输入数据逻辑信号的奇数个存储元件。 存储元件包括用于输出具有各自逻辑值的各个逻辑信号的输出线。 逻辑组合网络接收相应的逻辑信号，并且被配置为产生具有与从存储元件输出的逻辑信号的大部分相同的逻辑值的输出信号。 独占逻辑和电路接收从存储元件输出的相应逻辑信号，并且被配置为当从存储元件输出的逻辑信号之一经历逻辑值转换时，产生存储在存储元件中的逻辑数据信号的刷新 发生错误事件。
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公开(公告)号：US20180159317A1
公开(公告)日：2018-06-07
申请号：US15596465
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Bruno Mirabella , Francesco Pulvirenti , Salvatore Pappalardo
Abstract: A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.
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