公开(公告)号：US20230402980A1

公开(公告)日：2023-12-14

申请号：US17827293

申请日：2022-05-27

申请人： STMicroelectronics S.r.l.

发明人： Gaetano Cosentino

IPC分类号： H03F3/45 ,  H04B1/16 ,  H03F3/72

CPC分类号： H03F3/45179 ,  H04B1/16 ,  H03F2200/69 ,  H03F3/72 ,  H03F2203/45 ,  H03F3/4508

摘要： In an embodiment, a differential buffer includes: first and second input terminals configured to receive a differential input voltage; first and second output terminals configured to provide a differential output voltage; a differential source follower amplifier having first and second inputs respectively coupled to the first and second input terminals, and first and second outputs respectively coupled to the first and second output terminals; and a differential common source amplifier having first and second inputs respectively coupled to the second and first output terminals via a first pair of capacitors, and first and second outputs respectively coupled to the first and second output terminals.

公开(公告)号：US20230361737A1

公开(公告)日：2023-11-09

申请号：US18303931

申请日：2023-04-20

申请人： STMicroelectronics S.r.l.

发明人： Gaetano Cosentino

IPC分类号： H03F3/45 ,  H03F1/48 ,  H03F1/08

CPC分类号： H03F3/45475 ,  H03F3/45273 ,  H03F1/483 ,  H03F1/086

摘要： A circuit an amplifier stage that amplifier stage includes a positive amplifier branch and a negative amplifier branch and has current flow paths therethrough cascaded in a flow line for a core current for the amplifier stage between a supply node and a ground node. The positive and negative amplifier branches have respective input nodes configured to receive an input signal applied therebetween. A current mirror loop can be coupled to the respective input nodes of the positive and negative amplifier branches and provides an adjustable high-impedance bias source for the core current for the amplifier stage. In addition to, or instead of the current mirror loop, the circuit can include stability network having a gain bandwidth range. The amplifier stage is configured to short-circuit the output signal from the amplifier stage within the gain bandwidth range based on an output voltage setting signal.

公开(公告)号：US12088310B2

公开(公告)日：2024-09-10

申请号：US18192285

申请日：2023-03-29

申请人： STMicroelectronics S.r.l.

发明人： Davide Nicolo Fortunato ,  Antonino Calcagno ,  Marco Vinciguerra ,  Angelo Scuderi ,  Gaetano Cosentino

IPC分类号： H03L7/099 ,  H03L7/087 ,  H03L7/10 ,  H03L7/113

CPC分类号： H03L7/0992 ,  H03L7/087 ,  H03L7/099 ,  H03L7/103 ,  H03L7/113 ,  H03L2207/06

摘要： A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i−1 in the sequence.