公开(公告)号：US20030034827A1

公开(公告)日：2003-02-20

申请号：US10162135

申请日：2002-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro Pagliato ,  Paolo Rolandi ,  Giorgio Oddone ,  Marco Fontana

IPC: G05F003/02

CPC classification number: H02M3/073 ,  H02M2003/077

Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

公开(公告)号：US20020149089A1

公开(公告)日：2002-10-17

申请号：US10035006

申请日：2001-12-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Loris Vendrame ,  Paolo Caprara ,  Giorgio Oddone ,  Antonio Barcella

IPC: H01L029/00

CPC classification number: H01L29/7322 ,  H01L29/0813

Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (Pnull) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (Nnull) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (Pnull) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).

Abstract translation: 晶体管包括在相同类型（P）导电性的半导体材料层中具有导电性的第一类型（P）的衬底区域（14），至少第一类型（P +）的第一接触区域（13） 在衬底区域（14）内并且与晶体管的第一端子（C）相邻的导电性，位于衬底区域（14）内部的第二类型（N）导电体的阱（11），其中阱（11） 第二类型（N）的导电性包括与晶体管的第二端子（B）的区域相邻的至少第二导电类型（N +）的第二接触区域（12）和多个第三接触区域（10） ）通过适当的绝缘形状（20）与每个（10）和另一个（12）插入的晶体管的第三端子（E1，...，E3）的多个区域相邻的第一类型的导电性（P +）） 。