公开(公告)号：US20040037144A1

公开(公告)日：2004-02-26

申请号：US10438175

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Luigi Pascucci ,  Paolo Rolandi ,  Marco Riva

IPC: G11C007/00

CPC classification number: G11C11/5628

Abstract: A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 一种用于对多电平型非易失性存储器件进行编程的方法包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这些值与各个存储器字位要达到的阈值水平成正比，并有效地提供了在有限数量的脉冲结束时以寻求方式获得电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

公开(公告)号：US20030034827A1

公开(公告)日：2003-02-20

申请号：US10162135

申请日：2002-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro Pagliato ,  Paolo Rolandi ,  Giorgio Oddone ,  Marco Fontana

IPC: G05F003/02

CPC classification number: H02M3/073 ,  H02M2003/077

Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

公开(公告)号：US20040228179A1

公开(公告)日：2004-11-18

申请号：US10762195

申请日：2004-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

IPC: G11C016/28

CPC classification number: G11C16/28

Abstract: A parallel sense amplifier includes a measuring branch for receiving an input current to be measured, a plurality of reference branches each one for receiving a reference current, and a plurality of comparators each one for comparing a voltage at a measuring node along the measuring branch with a voltage at a reference node along a corresponding reference branch; the amplifier further includes a multiple current mirror for mirroring the input current into each reference branch.

Abstract translation: 并行读出放大器包括用于接收待测量的输入电流的测量分支，每个用于接收参考电流的多个参考分支;以及多个比较器，每个比较器用于将沿着测量分支的测量节点处的电压与 沿着相应参考分支的参考节点处的电压; 放大器还包括用于将输入电流镜像到每个参考分支中的多电流镜。

公开(公告)号：US20020163833A1

公开(公告)日：2002-11-07

申请号：US10179553

申请日：2002-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Paolo Rolandi

IPC: G11C011/34

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A nonvolatile memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines; and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract translation: 具有NOR结构的非易失性存储器具有存储器阵列，其包括以NOR形状排列成行和列的多个存储单元，布置在同一列上的存储单元连接到多个位线之一; 和列解码器。 列解码器包括多个选择级，每个选择级连接到相应的位线并且接收第一位线寻址信号。 选择级包括由第一位线寻址信号控制的字编程选择器，并将编程电压提供给每个选择级的仅一位位线。 每个选择级还包括由第二位线寻址信号控制的串编程选择电路，从而同时将编程电压提供给每个选择级的多个位线。

公开(公告)号：US20040130949A1

公开(公告)日：2004-07-08

申请号：US10742429

申请日：2003-12-19

Applicant: STMicroelectronics S.r.l.

Inventor： Paolo Rolandi

IPC: G11C016/04

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract translation: 一种非易失性存储器，其具有以NOR形式排列成存储器单元的行和列的存储器阵列，布置在同一列上的存储器单元连接到多个位线之一和列解码器。 列解码器包括多个选择级，每个选择级连接到相应的位线并且接收第一位线寻址信号。 选择级包括由第一位线寻址信号控制的字编程选择器，并将编程电压提供给每个选择级的仅一位位线。 每个选择级还包括由第二位线寻址信号控制的串编程选择电路，从而同时将编程电压提供给每个选择级的多个位线。