公开(公告)号：US20040263241A1

公开(公告)日：2004-12-30

申请号：US10874270

申请日：2004-06-24

申请人： NEC Electronics Corporation ,  NEC Corporation

发明人： Katsuyuki Fujikura ,  Katsumi Abe ,  Masamichi Shimoda

IPC分类号： G05F003/02

CPC分类号： G05F3/262

摘要： A current source circuit includes a voltage output section which outputs a voltage signal; a current source section and a conversion section. The current source section has at least one current source block comprising a plurality of current sources, each of which outputs an output current. The conversion section is provided between the voltage output section and the current source section and outputs a reference current to the plurality of current sources of the at least one current source block based on the voltage signal such that the output current from each of the plurality of current sources is set based on the reference current.

摘要翻译： 电流源电路包括：输出电压信号的电压输出部; 电流源部分和转换部分。 电流源部分具有包括多个电流源的至少一个电流源块，每个电流源输出输出电流。 转换部分设置在电压输出部分和电流源部分之间，并且基于电压信号将参考电流输出到至少一个电流源模块的多个电流源，使得来自多个 电流源基于参考电流设置。

公开(公告)号：US20040263237A1

公开(公告)日：2004-12-30

申请号：US10609360

申请日：2003-06-28

申请人： International Business Machines Corporation

发明人： Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

IPC分类号： G05F003/02

CPC分类号： H03K17/163 ,  H03K17/164

摘要： A semiconductor integrated circuit including a non-abrupt switching mechanism for a sleep transistor of a power gate structure to reduce ground bounce is provided. The semiconductor integrated circuit comprises a supply voltage line; a ground voltage line; a virtual ground voltage line; a logic circuit coupled to the supply voltage line and the virtual ground voltage line; at least one sleep transistor for controlling current flow to the logic circuit, the sleep transistor being coupled to the virtual ground voltage line and the ground voltage line; and a non-abrupt switching circuit for sequentially controlling the sleep transistor. The switching mechanism reduces the magnitude of voltage glitches on the power and ground rails as well as the minimum time required to stabilize power and ground.

摘要翻译： 提供一种包括用于减少地面反弹的功率门结构的休眠晶体管的非突变切换机构的半导体集成电路。 半导体集成电路包括电源电压线; 地电压线; 虚拟地电压线; 耦合到电源电压线和虚拟接地电压线的逻辑电路; 至少一个睡眠晶体管，用于控制到逻辑电路的电流，睡眠晶体管耦合到虚拟接地电压线和地电压线; 以及用于依次控制睡眠晶体管的非突变切换电路。 开关机构可以减少电源和接地导轨上的电压毛刺的大小以及稳定电源和接地所需的最短时间。

公开(公告)号：US20040246044A1

公开(公告)日：2004-12-09

申请号：US10823004

申请日：2004-04-13

发明人： Takao Myono ,  Yoshitaka Onaya

IPC分类号： G05F003/02

CPC分类号： H02M3/073 ,  H02M2003/075 ,  H02M2003/076

摘要： An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.

摘要翻译： 降低电荷泵电路运行开始时的浪涌电流，以防止对系统中其他电路的不利影响。 电荷转移MOS晶体管串联连接。 每个耦合电容器的一端连接到电荷转移MOS晶体管的每个连接点。 每个时钟驱动器的输出端施加在相应耦合电容器的另一端。 每个时钟驱动器包括具有比第一时钟驱动器更高的驱动能力的第一时钟驱动器和第二时钟驱动器。 每个时钟驱动器被控制，使得第一时钟驱动器在第一时间和在预定的经过时间结束时被停止并且第二时钟驱动器被投入运行。

公开(公告)号：US20040207459A1

公开(公告)日：2004-10-21

申请号：US10764997

申请日：2004-01-26

申请人： SynQor, Inc.

发明人： Thomas Farkas ,  Abram P. Dancy ,  Leif E. LaWhite ,  Martin F. Schlecht

IPC分类号： G05F003/02

CPC分类号： H02M3/07 ,  H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

摘要： A charge pump circuit in a gate controller provides a pumped gate control voltage to switches of a DC/DC converter. Different input voltages may be applied to the controller and an input voltage higher than the charge pump output could result in circuit damage. A clamp circuit between the input and output prevents the output voltage from being significantly below the input voltage to prevent such damage. The clamp circuit may be a transistor controlled by a comparator or amplifier.

摘要翻译： 栅极控制器中的电荷泵电路为DC / DC转换器的开关提供泵浦栅极控制电压。 不同的输入电压可以施加到控制器，并且高于电荷泵输出的输入电压可能导致电路损坏。 输入和输出之间的钳位电路可以防止输出电压明显低于输入电压，以防止这种损坏。 钳位电路可以是由比较器或放大器控制的晶体管。

公开(公告)号：US20040169547A1

公开(公告)日：2004-09-02

申请号：US10466697

申请日：2004-04-07

发明人： Phillip Matthew Jones ,  Christopher James Newton Fryer

IPC分类号： G05F003/02

CPC分类号： H05B33/08 ,  G09G3/30 ,  Y02B20/32

摘要： A high voltage AC power supply circuit for a capacitive load CL, such as an electroluminescent lamp, includes a low voltage DC supply, an inductor L and a FET S in series. The FET S can be pulsed so that the inductor L generates a voltage to charge the capacitive load CL via an H-bridge H, which is in parallel with the FET S. A diode D prevents current discharging from the capacitive load CL while the FET S is closed. The total capacitance downstream of the diode D and in parallel with the capacitive load CL is less than the capacitive load CL, so that when the polarity of the H-bridge is reversed, the voltage across the H-bridge collapses to earth and the capacitive load CL is discharged via the low voltage DC supply. The circuits which a employ a large smoothing capacitor in parallel with the H-bridge.

摘要翻译： 用于诸如电致发光灯的电容性负载CL的高压AC电源电路包括串联的低压DC电源，电感器L和FET S。 FET S可以被脉冲，使得电感器L产生电压，以通过与FET S并联的H桥H对电容负载CL充电。二极管D防止电容器从电容性负载CL放电，而FET S关闭。 二极管D下游并与电容性负载CL并联的总电容小于电容性负载CL，因此当H桥的极性反转时，H桥两端的电压塌陷至地，电容 负载CL通过低压直流电源放电。 使用与H桥并联的大平滑电容器的电路。

公开(公告)号：US20040155701A1

公开(公告)日：2004-08-12

申请号：US10728848

申请日：2003-12-08

申请人： Hynix Semiconductor Inc.

发明人： Kwang Hyun Kim ,  Young Jun Nam

IPC分类号： G05F003/02

CPC分类号： G05F1/465

摘要： An internal voltage generator of a semiconductor device features a tuning unit, a characteristic controller and an internal voltage generator. The tuning unit receives a test mode signal, an external signal and a signal stored in an internal setup device, and outputs a control signal. The characteristic controller receives the control signal, and outputs a characteristic controlling signal. The internal voltage generator receives a reference input signal and the characteristic controlling signal, and controls a characteristic of an internal voltage.

摘要翻译： 半导体器件的内部电压发生器具有调谐单元，特性控制器和内部电压发生器。 调谐单元接收测试模式信号，外部信号和存储在内部设置装置中的信号，并输出控制信号。 特征控制器接收控制信号，并输出特性控制信号。 内部电压发生器接收参考输入信号和特征控制信号，并控制内部电压的特性。

公开(公告)号：US20040155698A1

公开(公告)日：2004-08-12

申请号：US10769853

申请日：2004-02-03

发明人： Hajime Kimura

IPC分类号： G05F003/02

CPC分类号： H03K19/01728 ,  H03K19/01855

摘要： A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

摘要翻译： 提供可以正常工作而不管输入信号的二进制电位的数字电路。 一种包括校正单元和一个或多个电路元件的半导体器件，所述校正单元包括第一电容器，第二电容器，第一开关和第二开关，其中所述第一电容器的第一电极连接到输入 通过第一开关来控制向第一电容器的第二电极提供第一电位，通过第二开关来控制向第二电容器的第二电极提供第二电位，并且第二电位的电位 第一电容器的电极或第二电容器的第二电极的电位被提供给一个或多个电路元件。

公开(公告)号：US20040130386A1

公开(公告)日：2004-07-08

申请号：US10336738

申请日：2003-01-06

发明人： Han-Chi Liu ,  Wen-Cheng Yen

IPC分类号： G05F001/10 ,  G05F003/02

CPC分类号： G05F1/10

摘要： A reference voltage providing circuit. The operation amplifier includes a non-reverse input terminal, a reverse input terminal and an output terminal coupled to the reverse input terminal for outputting an output voltage. The reference voltage generator is coupled to the non-reverse input terminal. The loading is coupled to the output terminal. The current source provides a starting current. The switching device is coupled between the current source and the output terminal, and turned on by an accelerating charging signal to pass the starting current to the loading through the first output terminal. The pulse output device outputs the accelerating charging signal.

摘要翻译： 参考电压提供电路。 运算放大器包括非倒相输入端子，反向输入端子和耦合到反向输入端子的输出端子，用于输出输出电压。 参考电压发生器耦合到非反向输入端子。 负载耦合到输出端。 电流源提供启动电流。 开关装置耦合在电流源和输出端之间，并通过加速充电信号导通，以通过第一输出端将启动电流传递到负载。 脉冲输出装置输出加速充电信号。

公开(公告)号：US20040119528A1

公开(公告)日：2004-06-24

申请号：US10620834

申请日：2003-07-15

申请人： STMicroelectronics Limited

发明人： Tahir Rashid

IPC分类号： G05F003/02

CPC分类号： G05F3/225 ,  G05F3/30

摘要： The described embodiments of the invention relate to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

摘要翻译： 所描述的本发明的实施例涉及一种可以使用新的工艺技术制造的并且与旧的设计/产品兼容的电压参考发生器。 这通过引入电路来实现，以产生独立于主参考电压产生电路的偏移电压。

公开(公告)号：US20040051580A1

公开(公告)日：2004-03-18

申请号：US10407622

申请日：2003-04-03

申请人： Atmel Corporation

发明人： Giorgio Oddone ,  Lorenzo Bedarida ,  Mauro Chinosi

IPC分类号： G05F001/10 ,  G05F003/02

CPC分类号： G05F3/245

摘要： A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.