公开(公告)号：US20210050859A1

公开(公告)日：2021-02-18

申请号：US16993608

申请日：2020-08-14

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni SICURELLA ,  Manuela LA ROSA

IPC: H03M1/12 ,  H03M1/16 ,  H03M1/50 ,  H03K3/03 ,  G04F10/00

Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.

公开(公告)号：US20200287374A1

公开(公告)日：2020-09-10

申请号：US16882618

申请日：2020-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Manuela LA ROSA ,  Giovanni SICURELLA

IPC: H02H3/20 ,  H02H3/02 ,  H02H1/00 ,  H02H9/04 ,  H02H3/38 ,  H02H9/00 ,  H02H9/02

Abstract: A power stage in an electronic fuse circuit is driven by controller. The controller includes a first comparator set for output voltage control and a second comparator set for output current control. Each comparator set includes at least one comparator having a reference input, a feedback input, and one or more outputs. A driver circuit includes output terminals for driving the power stage. The driver circuit includes a switch that is selectively activated in response to outputs from the first and second comparator sets to clamp the voltage across the output terminals of the driver circuit. The clamp operation is made in response to feedback input to either of the first and second comparator sets having exceeded a certain reference.

公开(公告)号：US20190253039A1

公开(公告)日：2019-08-15

申请号：US16274987

申请日：2019-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni SICURELLA ,  Manuela LA ROSA

IPC: H03K3/011 ,  H03K5/24 ,  H03K19/20

Abstract: A voltage-to-time converter circuit receives a first voltage signal and produces a PWM-modulated signal having a duty-cycle proportional to the first voltage signal. A current integrator circuit receives the PWM-modulated signal from the voltage-to-time converter circuit block and produces an output signal by integrating a current signal from a current source over integration time intervals having a duration which is a function of the duty-cycle of the PWM-modulated signal. The current signal is proportional to a second voltage signal. The output signal is accordingly proportional to a product of the first voltage signal and the current signal, which is furthermore proportional to a product of the first voltage signal and the second voltage signal.

公开(公告)号：US20200076190A1

公开(公告)日：2020-03-05

申请号：US16555220

申请日：2019-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Manuela LA ROSA ,  Giovanni SICURELLA ,  Giuseppe MEOLA

IPC: H02H11/00 ,  G05F3/20

Abstract: An input node is configured to receive a supply signal which may be of a first polarity or a second polarity opposite the first polarity. A high input current circuit couples the input node to an output node through at least one power transistor having a control electrode. A low input current circuit couples a supply current from the input node to control circuit configured to control the power transistor. A circuit is provided to detect polarity reversal with respect to the supply signal. A protection circuit for the low input current circuit operates to decouple the control circuit from the input node if the supply signal has the second polarity. A protection circuit for the high input current circuit operates to short-circuit the control electrode of the power transistor to the current path provided by the power transistor between the input node and the output node.