公开(公告)号：US20230114535A1

公开(公告)日：2023-04-13

申请号：US17959619

申请日：2022-10-04

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo DE SANTA ,  Mauro MAZZOLA

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495

Abstract: A semiconductor die and an electrically conductive ribbon are arranged on a substrate. The electrically conductive ribbon includes a roughened surface. An insulating encapsulation is molded onto the semiconductor die and the electrically conductive ribbon. The roughened surface of the electrically conductive ribbon provides a roughened coupling interface to the insulating encapsulation.

公开(公告)号：US20240266259A1

公开(公告)日：2024-08-08

申请号：US18637906

申请日：2024-04-17

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro MAZZOLA ,  Matteo DE SANTA

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L23/4951 ,  H01L21/50 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/74

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.

公开(公告)号：US20180374780A1

公开(公告)日：2018-12-27

申请号：US16007767

申请日：2018-06-13

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mauro MAZZOLA ,  Matteo DE SANTA ,  Battista VITALI

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A process for manufacturing a semiconductor flip chip package and a corresponding flip chip package. The process comprises associating conducting bump pads to a face corresponding to an active side of one or more electronic dice, flipping the one or more electronic dice so that said face corresponding to an active side of one or more electronic dies is facing a leadframe carrying contacting pads in correspondence of said conducting bump pads, bonding said contacting pads to said conducting bump pads and encasing said one or more electronic dice in a casing by a molding operation. The process includes providing a leadframe having contacting pads presenting a recessed surface in correspondence of the position of said conducting bump pads.

公开(公告)号：US20240145351A1

公开(公告)日：2024-05-02

申请号：US18384524

申请日：2023-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo DE SANTA ,  Mauro MAZZOLA

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/49548 ,  H01L21/4842 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H05K1/181 ,  H05K3/3426 ,  H01L21/561

Abstract: A semiconductor die is arranged on a first surface of a leadframe having a first thickness between the first surface and a second surface opposite the first surface and an array of electrically conductive leads. Terminal recesses are provided in the electrically conductive leads in the array at the first surface. At the terminal recesses, the electrically conductive leads have a second thickness less than the first thickness. The semiconductor die is coupled with the electrically conductive leads via wires or ribbons having ends coupled to the electrically conductive leads arranged in the terminal recesses. The leadframe is partially cut starting from the second surface at the terminal recesses with a cutting depth between the first thickness and the second thickness. The partial cut produces exposed surfaces of the electrically conductive leads and the ends of the electrically conductive elongated formations providing wettable flanks for solder material.

公开(公告)号：US20230032786A1

公开(公告)日：2023-02-02

申请号：US17873749

申请日：2022-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo DE SANTA ,  Mirko ALESI

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07

Abstract: A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.

公开(公告)号：US20230005826A1

公开(公告)日：2023-01-05

申请号：US17848958

申请日：2022-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Riccardo VILLA ,  Matteo DE SANTA

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor chip is arranged over a substrate in the form of a leadframe. A set of current-carrying formations configured as conductive ribbons are coupled to the semiconductor chip. The substrate does not include electrically conductive formations for electrically coupling the conductive ribbons to each other. Electrical contacts are formed via wedge bonding, for instance, between adjacent ones of the conductive ribbons so that a contact is provided between the adjacent ones of the conductive ribbons in support of a multi-formation current-carrying channel.

公开(公告)号：US20210375726A1

公开(公告)日：2021-12-02

申请号：US17324436

申请日：2021-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro MAZZOLA ,  Matteo DE SANTA

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/50

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.