公开(公告)号：US20240363466A1

公开(公告)日：2024-10-31

申请号：US18309780

申请日：2023-04-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Salvacion Solas

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L21/561 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/85

Abstract: An example semiconductor device package includes a semiconductor die including an environmental sensor on a device side surface mounted to a package substrate; a barrier comprising a polyimide dry film photoresist material surrounding the environmental sensor on the device side surface of the semiconductor die, the barrier having an interior side facing the environmental sensor and having an opposing exterior side; electrical connections between bond pads on the semiconductor die and leads on the package substrate; and mold compound covering portions of the semiconductor die and contacting the exterior side of the barrier, the mold compound covering the electrical connections and portions of the package substrate, with portions of the leads of the package substrate exposed from the mold compound to form terminals of the semiconductor device package, and the environmental sensor in a sensor cavity formed by the barrier and exposed from the mold compound.

公开(公告)号：US20240339444A1

公开(公告)日：2024-10-10

申请号：US18749794

申请日：2024-06-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xuan Liang ,  Meili Wang ,  Fei Wang ,  Xue Dong ,  Qi Qi

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/05 ,  H01L24/06 ,  H01L24/46 ,  H01L2224/04042 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0568 ,  H01L2224/0603 ,  H01L2224/08145 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48106 ,  H01L2224/48141 ,  H01L2224/48992 ,  H01L2224/85007 ,  H01L2924/0132 ,  H01L2924/12041

Abstract: A light-emitting substrate is provided, including first and second substrates opposite to each other, and a bonding wire structure including a bonding wire. The first substrate includes: a first base substrate and a first conductive pad. The second substrate includes a second base substrate and a second conductive pad. The first conductive pad is on a surface of the first substrate away from the second substrate, the second conductive pad is on a surface of the second substrate away from the first substrate. The bonding wire is soldered to the first conductive pad at a first solder joint and to the second conductive pad at a second solder joint. The bonding wire includes, at each of the first solder joint and the second solder joint, a portion having an angle with a plane where the first base substrate is located and/or having a curved arc.

公开(公告)号：US20240321802A1

公开(公告)日：2024-09-26

申请号：US18187180

申请日：2023-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JUNYAN TANG ,  SUNGJUN CHUN ,  DANIEL MARK DREPS ,  WIREN DALE BECKER ,  JOSE A HEJASE ,  PAVEL ROY PALADHI ,  NAM HUU PHAM

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L24/20 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/45 ,  H01L24/85 ,  H01L2924/1432

Abstract: An integrated circuit and a cable interconnect interface are disposed on a substrate and in communication with one another. The cable interconnect interface includes a first plurality of connector pads arranged in a first column and a second plurality of connector pads arranged in a second column. A radio frequency absorption layer is disposed on one or more of the first plurality of connector pads and the second plurality of connector pads. The first plurality of connector pads includes a first group of transmission connector pads and a first group of receiving connector pads. The second plurality of connector pads includes a second group of transmission connector pads and a second group of receiving connector pads. The first group of transmission connector pads is opposite the second group of transmission connector pads, and the first group of receiving connector pads is opposite the second group of receiving connector pads.

公开(公告)号：US20240312976A1

公开(公告)日：2024-09-19

申请号：US18596514

申请日：2024-03-05

Applicant: Kioxia Corporation

Inventor： Keiichi NIWA

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/3135 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13 ,  H01L24/16 ,  H01L24/33 ,  H01L24/49 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/85205 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2924/0665

Abstract: A semiconductor device includes a wiring board including first and second surfaces opposite to each other, a first semiconductor element on the first surface side of the wiring board, a second semiconductor element adjacent to the first semiconductor element on the first surface side of the wiring board, a first resin composition on the first surface side of the wiring board, and a second resin composition that covers the first and second semiconductor elements and the first resin composition. The first resin composition includes a first part between the first surface of the wiring board and a surface of the first semiconductor element facing the first surface, and a second part contacting a first side surface of the second semiconductor element facing the first semiconductor element.

公开(公告)号：US20240304607A1

公开(公告)日：2024-09-12

申请号：US18596528

申请日：2024-03-05

Applicant: Kioxia Corporation

Inventor： Kazuma HASEGAWA

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H10B80/00 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/85801 ,  H01L2224/96 ,  H01L2225/1052 ,  H01L2924/1438

Abstract: A semiconductor device includes a substrate that includes a first surface, a first semiconductor chip that includes a second surface facing the first surface of the substrate and a third surface opposite to the second surface, each of the second and third surfaces having a rectangular shape that includes a plurality of sides and has surface areas that are different, and a second semiconductor chip disposed on the first surface of the substrate on one side of the first semiconductor chip. When viewed in a first direction substantially perpendicular to the substrate, one of the sides of the third surface that is closest to the second semiconductor chip overlaps an interior portion of the second semiconductor chip.

公开(公告)号：US12087673B2

公开(公告)日：2024-09-10

申请号：US17983249

申请日：2022-11-08

Applicant: Texas Instruments Incorporated

Inventor： Abram Castro ,  Usman Chaudhry ,  Joe Adam Garcia ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/67 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/67138 ,  H01L23/3121 ,  H01L23/49541 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/3494 ,  H01L22/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/3511 ,  H05K2201/10636

Abstract: An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

公开(公告)号：US12087652B2

公开(公告)日：2024-09-10

申请号：US17884515

申请日：2022-08-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yi Chen ,  Chang-Lin Yeh ,  Jen-Chieh Kao

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/10 ,  H01L23/498 ,  H01L23/66 ,  H01Q1/22 ,  H01Q13/10 ,  H01Q19/10 ,  H01Q21/06

CPC classification number: H01L23/3114 ,  H01L23/10 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/66 ,  H01L24/13 ,  H01L24/73 ,  H01L24/85 ,  H01Q1/2283 ,  H01Q1/2291 ,  H01Q13/10 ,  H01Q19/10 ,  H01Q21/061 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.

公开(公告)号：US12068261B2

公开(公告)日：2024-08-20

申请号：US17822960

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory Thomas Ostrowicki ,  Amit Sureshkumar Nangia

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/647 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48245

Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

公开(公告)号：US20240274583A1

公开(公告)日：2024-08-15

申请号：US18514107

申请日：2023-11-20

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

公开(公告)号：US12057431B2

公开(公告)日：2024-08-06

申请号：US17550729

申请日：2021-12-14

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Basil Milton ,  Romeo Olida ,  Jonathan Geller ,  Tomer Levinson

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L24/43 ,  H01L24/78 ,  H01L2224/4383 ,  H01L2224/43985 ,  H01L2224/7825 ,  H01L2224/78343 ,  H01L2224/7855 ,  H01L2224/85035 ,  H01L2224/85047 ,  H01L2224/85205

Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.