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1.发明授权公开(公告)号：US11322201B2
公开(公告)日：2022-05-03
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
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Patent Agency Ranking
公开(公告)号：US20210383865A1
公开(公告)日：2021-12-09
申请号：US17410141
申请日：2021-08-24
Applicant: STMicroelectronics S.r.l.
Inventor： Michele La Placa , Fabio Enrico Carlo Disegni , Federico Goller
Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.
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公开(公告)号：US11107525B2
公开(公告)日：2021-08-31
申请号：US16924760
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Michele La Placa , Fabio Enrico Carlo Disegni , Federico Goller
Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.
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4.发明申请公开(公告)号：US20210233582A1
公开(公告)日：2021-07-29
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
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公开(公告)号：US11557340B2
公开(公告)日：2023-01-17
申请号：US17410141
申请日：2021-08-24
Applicant: STMicroelectronics S.r.l.
Inventor： Michele La Placa , Fabio Enrico Carlo Disegni , Federico Goller
Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.
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公开(公告)号：US20210012836A1
公开(公告)日：2021-01-14
申请号：US16924760
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Michele La Placa , Fabio Enrico Carlo Disegni , Federico Goller
Abstract: A voltage regulator and a phase change memory are disclosed. In an embodiment a phase-change memory includes an array of a plurality of phase-change memory cells, an address decoder configured for receiving an address signal and selecting a sub-area in the array of the plurality of memory cells, the selected sub-area having a given number of bits of a data signal and a writing circuit including a control circuit configured for receiving the data signal and determining, for each memory cell in the selected sub-area, whether a respective bit of the data signal indicates that the memory cell is to be changed from the amorphous state to the polycrystalline state and one or more driving circuits supplied via a regulated voltage and configured for applying the set current for the first interval to the memory cells that are to be changed from the amorphous state to the polycrystalline state.
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