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公开(公告)号：US11355191B2
公开(公告)日：2022-06-07
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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公开(公告)号：US10720223B2
公开(公告)日：2020-07-21
申请号：US15484500
申请日：2017-04-11
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Giuseppe Castagna
IPC: G11C29/02 , G11C29/56 , G11C29/50 , G01R31/3187 , G06F11/22 , G06F11/30 , G06F11/34 , G11C16/04
Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.
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公开(公告)号：US10186317B2
公开(公告)日：2019-01-22
申请号：US15842347
申请日：2017-12-14
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Francesco Perroni , Carmelo Paolino , Salvatore Polizzi
Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
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公开(公告)号：US20180096727A1
公开(公告)日：2018-04-05
申请号：US15474607
申请日：2017-03-30
Applicant: STMicroelectronics S.r.l.
Inventor： Salvatore Polizzi , Maurizio Francesco Perroni
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C8/10 , G11C11/1657 , G11C11/1659 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C13/0097 , G11C2213/79 , G11C2213/82
Abstract: An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.
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公开(公告)号：US20180061499A1
公开(公告)日：2018-03-01
申请号：US15804790
申请日：2017-11-06
Applicant: STMicroelectronics S.r.l.
IPC: G11C16/28 , G11C5/14 , G11C16/24 , G11C16/14 , G11C16/10 , G11C16/30 , G05F3/24 , G11C7/14 , G11C7/12 , G11C16/08 , G11C7/04 , G11C8/10
CPC classification number: G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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Patent Agency Ranking
公开(公告)号：US09830995B2
公开(公告)日：2017-11-28
申请号：US15140796
申请日：2016-04-28
Applicant: STMicroelectronics S.r.l.
IPC: G11C16/28 , G05F3/24 , G11C5/14 , G11C7/12 , G11C7/14 , G11C16/24 , G11C16/30 , G11C16/08 , G11C16/10 , G11C16/14 , G11C7/04 , G11C8/10
CPC classification number: G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
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公开(公告)号：US20170062064A1
公开(公告)日：2017-03-02
申请号：US15140796
申请日：2016-04-28
Applicant: STMicroelectronics S.r.l
CPC classification number: G11C16/28 , G05F3/245 , G11C5/147 , G11C7/04 , G11C7/12 , G11C7/14 , G11C8/10 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/30
Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
Abstract translation: 用于偏置非易失性存储单元的电路包括全局偏置线和偏置节点之间的虚拟解码路径，耦合到虚拟解码路径并被配置为提供参考电流的参考电流发生器，被配置为设置单元 偏置节点上的偏置电压，以及补偿级，被配置为补偿偏置节点处的偏置级的电流吸收，使得参考电流将流过虚拟解码路径。
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公开(公告)号：US20210183442A1
公开(公告)日：2021-06-17
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
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公开(公告)号：US20210125668A1
公开(公告)日：2021-04-29
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
IPC: G11C13/00
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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10.发明申请公开(公告)号：US20170213580A1
公开(公告)日：2017-07-27
申请号：US15477695
申请日：2017-04-03
Applicant: STMicroelectronics S.r.l
Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.
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