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公开(公告)号:US11615857B2
公开(公告)日:2023-03-28
申请号:US17224024
申请日:2021-04-06
Inventor: Francesco La Rosa , Enrico Castaldo , Francesca Grande , Santi Nunzio Antonino Pagano , Giuseppe Nastasi , Franco Italiano
Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.
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2.
公开(公告)号:US10297292B2
公开(公告)日:2019-05-21
申请号:US15620325
申请日:2017-06-12
Applicant: STMicroelectronics S.r.l.
Inventor: Antonino Conte , Mario Micciche' , Santi Nunzio Antonino Pagano
Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
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3.
公开(公告)号:US20170278552A1
公开(公告)日:2017-09-28
申请号:US15620325
申请日:2017-06-12
Applicant: STMicroelectronics S.r.l.
Inventor: Antonino Conte , Mario Micciche' , Santi Nunzio Antonino Pagano
CPC classification number: G11C7/062 , G11C7/1051 , G11C7/12 , G11C16/24 , G11C16/28 , G11C2207/002
Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
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