公开(公告)号：US20230170006A1

公开(公告)日：2023-06-01

申请号：US18056803

申请日：2022-11-18

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N. V. ,  STMicroelectronics Application GMBH

发明人： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC分类号： G11C7/24 ,  G11C7/10

CPC分类号： G11C7/24 ,  G11C7/1039 ,  G11C7/1069

摘要： In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US12068057B2

公开(公告)日：2024-08-20

申请号：US18056803

申请日：2022-11-18

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

发明人： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC分类号： G11C7/24 ,  G11C7/10

CPC分类号： G11C7/24 ,  G11C7/1039 ,  G11C7/1069

摘要： In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.