-
公开(公告)号：US12117942B2
公开(公告)日：2024-10-15
申请号：US18109675
申请日：2023-02-14
Applicant: STMicroelectronics S.r.l. , STMicroelectronics SA
Inventor： Roberta Vittimani , Federico Goller , Riccardo Angrilli , Charles Aubenas
IPC: G06F12/14
CPC classification number: G06F12/1441 , G06F12/1458
Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.
-
2.发明申请公开(公告)号：US20190007202A1
公开(公告)日：2019-01-03
申请号：US16022110
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
-
公开(公告)号：US11210161B2
公开(公告)日：2021-12-28
申请号：US16928768
申请日：2020-07-14
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
-
Patent Agency Ranking
公开(公告)号：US12210880B2
公开(公告)日：2025-01-28
申请号：US17587887
申请日：2022-01-28
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Roberta Vittimani , Martina Trogu
IPC: G06F9/4401 , G11C7/10 , G11C7/20 , G11C8/06 , G11C29/42
Abstract: A device includes an interface, which, in operation, couples to a non-volatile memory. The device includes circuitry coupled to the interface. The circuitry, in operation: reads a data configuration structure stored on the non-volatile memory, the data configuration structure being associated with a client circuit of a plurality of client circuits; and configures the client circuit, the configuring including writing data words of the data configuration structure to the client circuit, the writing including determining an address of the client circuit, the address being associated with at least one of the data words, the determining being based on number of data words in the data configuration structure.
-
公开(公告)号：US11057194B2
公开(公告)日：2021-07-06
申请号：US16022033
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
-
公开(公告)号：US11032067B2
公开(公告)日：2021-06-08
申请号：US16022110
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
-
公开(公告)号：US20200341836A1
公开(公告)日：2020-10-29
申请号：US16928768
申请日：2020-07-14
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
-
公开(公告)号：US20190007201A1
公开(公告)日：2019-01-03
申请号：US16022033
申请日：2018-06-28
Inventor： Roberto Colombo , Guido Marco Bertoni , William Orlando , Roberta Vittimani
Abstract: A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.016 seconds)
