公开(公告)号：US20030016563A1

公开(公告)日：2003-01-23

申请号：US10178081

申请日：2002-06-21

Applicant: STMicroelectronics SA

Inventor： Christophe Frey

IPC: G11C005/00

CPC classification number: G11C11/41

Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between a first node linked to a bit line and a second node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.

Abstract translation: 存储单元形成有缓冲电路。 缓冲电路的输出端与输入端相连，构成逻辑锁存器。 写访问晶体管设置在链接到位线的第一节点和缓冲电路的输入之间。 写访问晶体管的控制栅极链接到链接到写字线的第二节点，并且读访问晶体管设置在链接到位线的第一节点和链接到读字线的第二节点之间。 读取存取晶体管的控制栅极连接到缓冲电路的输出端。