公开(公告)号：US20160181382A1

公开(公告)日：2016-06-23

申请号：US14577656

申请日：2014-12-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  David Barge

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/41783 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.

Abstract translation: 一种用于形成晶体管的方法包括在绝缘体上硅（SOI）衬底的第一半导体层的顶表面上限定玛瑙结构。 门结构包括绝缘盖。 然后共形沉积第二半导体层。 沉积的第二半导体层包括在第一半导体层的表面上的外延部分和绝缘盖表面上的非晶部分。 然后使用选择性蚀刻除去非晶部分。 剩余的外延部分在晶体管栅极结构的任一侧上形成刻面凸起的源极 - 漏极结构。 用于小平面的倾斜表面的斜率取决于在保形沉积期间使用的工艺参数。

公开(公告)号：US09412589B2

公开(公告)日：2016-08-09

申请号：US14501639

申请日：2014-09-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David Barge ,  Philippe Garnier ,  Yves Campidelli

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02609 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract translation: 集成电路包括在SOI衬底的不同区域上的NMOS晶体管和PMOS晶体管。 每个晶体管包括栅极区域，在栅极区域的侧面上的多层横向绝缘区域，同时也在衬底上。 每个多层横向绝缘区域包括远离基板倾斜的倾斜部分。 源区和漏区在衬底上，并通过相应的多层横向绝缘区与栅极区的侧面分离。 源极和漏极区域具有靠在横向绝缘区域的倾斜部分的倾斜部分。

公开(公告)号：US09269768B2

公开(公告)日：2016-02-23

申请号：US14605064

申请日：2015-01-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David Barge ,  Pierre Morin

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L29/0653 ,  H01L21/76283 ,  H01L27/1203

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.