公开(公告)号：US20230058759A1

公开(公告)日：2023-02-23

申请号：US17406164

申请日：2021-08-19

Applicant: Synaptics Incorporated

Inventor： Yoshihiko Hori ,  Takefumi Seno ,  Takashi Tamura ,  Kazuhiko Kanda

IPC: H04L25/02 ,  H04B1/16 ,  H04B1/18

Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

公开(公告)号：US10972317B2

公开(公告)日：2021-04-06

申请号：US16287720

申请日：2019-02-27

Applicant: SYNAPTICS INCORPORATED

Inventor： Takefumi Seno

IPC: H04B3/00 ,  H04L25/02 ,  H04L7/027 ,  H04L7/033

Abstract: A receiver device comprises one or more differential receivers configured to respectively output single ended signals, one or more delay compensation circuitries configured to delay the single ended signals, clock recovery circuitry configured to generate a recovered clock signal based on a compensated single ended signals respectively outputted from the delay compensation circuitries, and one or more latch circuitries configured to respectively latch the compensated single ended signals in synchronization with the recovered clock signal.

公开(公告)号：US11646915B2

公开(公告)日：2023-05-09

申请号：US17406164

申请日：2021-08-19

Applicant: Synaptics Incorporated

Inventor： Yoshihiko Hori ,  Takefumi Seno ,  Takashi Tamura ,  Kazuhiko Kanda

IPC: H04L25/02 ,  H04B1/18 ,  H04B1/16

CPC classification number: H04L25/0276 ,  H04B1/1607 ,  H04B1/18

Abstract: An integrated circuit includes a plurality of signal inputs, a receiver, calibration circuitry, and input switch circuitry. The receiver includes differential input terminals. The calibration circuitry is configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being placed in a calibration mode. The input switch circuitry is configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being placed in a mode different from the calibration mode. The input switch circuitry is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being placed in the calibration mode.

公开(公告)号：US11830461B2

公开(公告)日：2023-11-28

申请号：US16720858

申请日：2019-12-19

Applicant: SYNAPTICS INCORPORATED

Inventor： Tsuyoshi Kuroiwa ,  Hirokazu Hatayama ,  Takefumi Seno

IPC: G09G5/393

CPC classification number: G09G5/393 ,  G09G2310/0286 ,  G09G2310/062 ,  G09G2310/08

Abstract: A display driver comprises an interface and signal supply circuitry. The interface is configured to receive image data. The signal supply circuitry is configured to supply at least one drive control signal to a display panel based on a detection of a data error in the image data associated with a first horizontal line in a first vertical sync period, causing a first pixel circuit and a second pixel circuit hold, in the first vertical sync period, first hold voltages based in part on at least one drive control signal and second hold voltages held in a second vertical sync period prior to the first vertical sync period. The first pixel circuit is associated with the first horizontal line, and the second pixel circuit is associated with a second horizontal line and driven after the first pixel circuit.

公开(公告)号：US11171111B2

公开(公告)日：2021-11-09

申请号：US16753758

申请日：2018-10-02

Applicant: Synaptics Incorporated

Inventor： Kazuhiro Okamura ,  Takeshi Okubo ,  Yuichi Nakagomi ,  Takefumi Seno

IPC: H01L23/00

Abstract: An integrated circuit device comprises: a resin film that is flexible; a plurality of traces bonded on a surface of the resin film and arrayed in a specific direction; an IC chip bonded on the surface of the resin film, located offset to the traces in a direction perpendicular to the specific direction, and connected to the traces; and a protection pattern formed on the surface of the resin film, located in the specific direction with respect to a disposition region in which the IC chip and/or the traces are disposed, and formed of the same material as that of the traces.