公开(公告)号：US07550329B2

公开(公告)日：2009-06-23

申请号：US12119707

申请日：2008-05-13

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US20050104069A1

公开(公告)日：2005-05-19

申请号：US10954524

申请日：2004-09-29

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： G02F1/1368 ,  G02F1/136 ,  G09F9/30 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US07151279B2

公开(公告)日：2006-12-19

申请号：US10954524

申请日：2004-09-29

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

公开(公告)号：US20080210943A1

公开(公告)日：2008-09-04

申请号：US12119707

申请日：2008-05-13

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L27/088

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US07408200B2

公开(公告)日：2008-08-05

申请号：US11612141

申请日：2006-12-18

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： H01L33/00

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US20070091220A1

公开(公告)日：2007-04-26

申请号：US11612141

申请日：2006-12-18

申请人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

发明人： Sahng-Ik Jun ,  Jae-Hong Jeon ,  Kwon-Young Choi ,  Jeong-Young Lee

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：基板; 形成在所述基板上的第一信号线; 形成在所述基板上并与所述第一信号线相交的第二信号线; 薄膜晶体管，包括连接到第一信号线的栅极，并且具有基本上平行于第一信号线的边缘，连接到第二信号线的源电极和与栅电极的边缘重叠的漏电极; 以及连接到漏电极的像素电极。

公开(公告)号：US07320906B2

公开(公告)日：2008-01-22

申请号：US10922343

申请日：2004-08-19

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC分类号： H01L21/84

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US07566906B2

公开(公告)日：2009-07-28

申请号：US11958230

申请日：2007-12-17

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  San-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  San-Jin Jeon

IPC分类号： H01L29/04

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上的半导体层; 形成在所述半导体层上的多个欧姆接触; 源极和漏极形成在欧姆接触上; 形成在源电极和漏电极上的钝化层，具有露出漏电极的一部分的第一接触孔和露出半导体层的第一部分并且具有与源电极和漏电极的边缘重合的边缘的开口; 以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。

公开(公告)号：US07459323B2

公开(公告)日：2008-12-02

申请号：US11512805

申请日：2006-08-30

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L21/00

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20050082535A1

公开(公告)日：2005-04-21

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1368 ,  G03C1/85 ,  G03C5/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。