公开(公告)号：US06222751B1

公开(公告)日：2001-04-24

申请号：US09571354

申请日：2000-05-15

申请人： Salvatore Portaluri ,  Alessandro Savo ,  Maurizio Nessi ,  Luigi Eugenio Garbelli ,  Giorgio Sciacca

发明人： Salvatore Portaluri ,  Alessandro Savo ,  Maurizio Nessi ,  Luigi Eugenio Garbelli ,  Giorgio Sciacca

IPC分类号： H02M75387

CPC分类号： H03K17/166 ,  H02M7/53803

摘要： A driver circuit includes a half-bridge output stage including two transistors with a common terminal for connection as the driver output to a coil of a DC motor. Two amplifiers drive the transistors in the push-pull operation and two capacitors are connected between the driver output and one input of a respective amplifier to form feedback loops for controlling the output slew-rate. Two current generators are selectively connected to an input of either of the amplifiers through respective pairs of switches. A commutation sequencer turns on and off the switches according to a commutation program. Comparators are connected to the drive output for detecting predetermined output voltage conditions and providing the commutation sequencer with signals for conditioning the commutation program as a function of the detected voltage conditions.

摘要翻译： 驱动器电路包括半桥输出级，其包括具有用于连接的公共端子的两个晶体管，因为驱动器输出到直流电动机的线圈。 两个放大器在推挽操作中驱动晶体管，并且两个电容器连接在驱动器输出和相应放大器的一个输入端之间，以形成用于控制输出转换速率的反馈回路。 两个电流发生器通过相应的开关对选择性地连接到任一放大器的输入。 换向顺序器根据换向程序打开和关闭开关。 比较器连接到驱动输出端，用于检测预定的输出电压状况，并根据检测到的电压条件向换向定序器提供用于调节换向程序的信号。

公开(公告)号：US06392375B1

公开(公告)日：2002-05-21

申请号：US09542101

申请日：2000-04-04

申请人： Salvatore Portaluri ,  Alessandro Savo ,  Luigi Eugenio Garbelli ,  Giuseppe Luciano ,  Luca Schillaci

发明人： Salvatore Portaluri ,  Alessandro Savo ,  Luigi Eugenio Garbelli ,  Giuseppe Luciano ,  Luca Schillaci

IPC分类号： H02P100

CPC分类号： G11B5/4846 ,  G11B5/4813 ,  G11B5/5526 ,  G11B21/083 ,  H02P25/034

摘要： The method is for controlling a voice coil motor which drives a mechanical arm via a control circuit which sets the output nodes, to which the motor is connected, in a high impedance state for a certain time interval. The method and circuit detect the back electromotive force induced on the motor winding during the time interval, and deliver current pulses for driving the motor. The circuit compares the detected back electromotive force with a certain target value and regulates the amplitude of the driving current pulses as a function of the difference between the detected value of the back electromotive force and a voltage signal representing the desired speed of the arm, according to a pre-established function. A preferred embodiment includes such a function being a pre-established saturated linear characteristic with an offset value.

摘要翻译： 该方法用于控制音圈电动机，其经由控制电路驱动机械臂，该控制电路将电动机连接的输出节点设置在高阻抗状态下一段时间间隔。 该方法和电路在时间间隔内检测在电动机绕组上感应的反电动势，并传送用于驱动电动机的电流脉冲。 该电路将检测到的反电动势与某一目标值进行比较，并且将驱动电流脉冲的幅度作为反电动势的检测值与表示臂的期望速度的电压信号之间的差的函数进行比较，根据 到一个预先建立的功能。 优选实施例包括具有偏移值的预先建立的饱和线性特性的功能。

公开(公告)号：US06246289B1

公开(公告)日：2001-06-12

申请号：US09507562

申请日：2000-02-18

申请人： Valerio Pisati ,  Salvatore Portaluri ,  Alessandro Savo ,  Stefano Marchese

发明人： Valerio Pisati ,  Salvatore Portaluri ,  Alessandro Savo ,  Stefano Marchese

IPC分类号： H03F345

CPC分类号： H03G1/0023

摘要： A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors. The amplifier further includes two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.

摘要翻译： 一种具有宽带宽和相位变化较小的可编程增益多级放大器，具有由第一电流源偏置的差分输入级，馈送差分电压信号，该级连接到阴极端子连接的一对二极管 到由双极晶体管的集电极端子提供的由第二电流源偏置并且其中集电极端子连接到负载电阻器的各个双极晶体管，放大器的差分输出被提供。 放大器还包括两个电路分支，每个电路分支由双极晶体管和第三电流源构成，第三电流源分别连接到双极晶体管的集电极端子和发射极端子，其中基极端子接收差分电压信号 并且集电极端子连接到两个二极管中的相应一个的阴极端子，电路分支通过一对电容器相互连接。

公开(公告)号：US6037838A

公开(公告)日：2000-03-14

申请号：US264296

申请日：1999-03-08

申请人： Stefano Marchese ,  Valerio Pisati ,  Salvatore Portaluri ,  Alessandro Savo

发明人： Stefano Marchese ,  Valerio Pisati ,  Salvatore Portaluri ,  Alessandro Savo

IPC分类号： H03G1/00 ,  H03G7/06 ,  H03F3/45 ,  H03G7/00

CPC分类号： H03G7/06 ,  H03G1/0023

摘要： An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.

摘要翻译： 在高频下具有可编程增益和输入线性度的放大器可以增加增益，而不会影响输入线性度并且不会显着增加电流消耗。 放大器包括输入级，其接收用于通过压缩执行其电流转换的电压信号。 输出级连接到输入级，并且解压缩由输入级提供的信号，以产生其增益放大。 放大器还包括插入在输入级和输出级之间的至少一个电流放大器级。 至少一个电流放大器包括串联连接到负载二极管和电流源的至少一个双极晶体管。 在所述至少一个放大器级中提供所述负载二极管的跨导的减小以确定所述放大器的可编程增益因子。

公开(公告)号：US06316926B1

公开(公告)日：2001-11-13

申请号：US09575334

申请日：2000-05-19

申请人： Alessandro Savo ,  Salvatore Portaluri ,  Pierandrea Savo ,  Giuseppe Luciano

发明人： Alessandro Savo ,  Salvatore Portaluri ,  Pierandrea Savo ,  Giuseppe Luciano

IPC分类号： G05F140

CPC分类号： H02M1/36 ,  Y10S323/901

摘要： A switching regulator having a switching element, a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation.

摘要翻译： 具有开关元件的开关调节器，用于根据开关调节器输出电量与目标输出电量之间的差异来改变开关元件的占空比的控制回路和用于数字控制所述开关元件的数字软启动电路 独立于所述差值的开关元件的占空比在开关调节器操作的启动阶段。

公开(公告)号：US06496550B1

公开(公告)日：2002-12-17

申请号：US09444340

申请日：1999-11-19

申请人： Melchiorre Bruccoleri ,  Marco Demicheli ,  Daniele Ottini ,  Alessandro Savo

发明人： Melchiorre Bruccoleri ,  Marco Demicheli ,  Daniele Ottini ,  Alessandro Savo

IPC分类号： H04L2708

CPC分类号： G11B20/10277 ,  G11B20/10509

摘要： A read and analog-to-digital data conversion channel includes an input circuit receiving an input data stream, and a time interleaved analog-to-digital converter connected to the input circuit. The time interleaved analog-to-digital converter includes a pair of analog-to-digital converters functioning in parallel and at half the clock frequency. A signal path through the time interleaved analog-to-digital converter is subdivided into two parallel paths through the pair of analog-to-digital converters. There is a first path for even bits and a second path for odd bits. A digital post-processing circuit is connected to the two parallel paths of the time interleaved analog-to-digital converter, and has an output providing a reconstructed data stream. At least one adjusting digital-to-analog converter is connected between the digital post-processing circuit and the input circuit for control thereof. The conversion channel further includes an offset circuit for compensating an offset in the pair of analog-to-digital converters in the time interleaved analog-to-digital converter. The offset circuit is controlled by the digital post-processing circuit, and includes first and second distinct offset compensating circuits independently controlled by the digital post-processing circuit.

摘要翻译： 读取和模数转换数据转换通道包括接收输入数据流的输入电路和连接到输入电路的时间交错模数转换器。 时间交织的模数转换器包括并行和半个时钟频率工作的一对模 - 数转换器。 通过时间交织的模数转换器的信号路径被分成通过该对模数转换器的两条并行路径。 有一个偶数位的第一个路径，奇数位的第二个路径。 数字后处理电路连接到时间交错模数转换器的两个并行路径，并且具有提供重构数据流的输出。 至少一个调节数模转换器连接在数字后处理电路和输入电路之间，用于控制。 转换通道还包括用于补偿时间交织模数转换器中的该对模数转换器中的偏移的偏移电路。 偏移电路由数字后处理电路控制，并且包括由数字后处理电路独立控制的第一和第二不同偏移补偿电路。

公开(公告)号：US08232846B1

公开(公告)日：2012-07-31

申请号：US12713069

申请日：2010-02-25

申请人： Giuseppe De Vita ,  Alessandro Savo

发明人： Giuseppe De Vita ,  Alessandro Savo

IPC分类号： H03K3/26

CPC分类号： H03K4/502

摘要： In one embodiment, an RC oscillator is provided. The oscillator includes a current generator circuit configured to generate a current. A capacitor is configured to be charged by the current. An inverter includes an input coupled to the capacitor. An output of the inverter goes high when a voltage across the capacitor reaches a threshold voltage of the inverter. A switch coupled to the output of the inverter and the capacitor is configured to close when the output of the inverter goes high. This discharges the capacitor. The output of the inverter goes low when the capacitor is discharged and the switch is opened. Clock generator logic is configured to receive the output of the inverter and generate a clock signal. The current is proportional to the threshold voltage of the inverter.

摘要翻译： 在一个实施例中，提供了RC振荡器。 振荡器包括被配置为产生电流的电流发生器电路。 电容器被配置为由电流充电。 反相器包括耦合到电容器的输入端。 当电容器两端的电压达到逆变器的阈值电压时，变频器的输出变为高电平。 耦合到逆变器和电容器的输出的开关被配置为当逆变器的输出变高时闭合。 这会使电容器放电。 当电容器放电并且开关打开时，变频器的输出变为低电平。 时钟发生器逻辑被配置为接收反相器的输出并产生时钟信号。 电流与变频器的门限电压成比例。

公开(公告)号：US08902008B1

公开(公告)日：2014-12-02

申请号：US13548670

申请日：2012-07-13

申请人： Giuseppe De Vita ,  Alessandro Savo

发明人： Giuseppe De Vita ,  Alessandro Savo

IPC分类号： H03K3/26

CPC分类号： H03K4/502

摘要： Aspects of the disclosure provide a circuit. The circuit includes a current generator, a capacitor, a comparator, a switch and a clock generator logic. The current generator is configured to generate a current proportional to a comparator threshold voltage by a ratio. The capacitor is configured to be charged by the current to have a capacitor voltage. The comparator is configured to compare the capacitor voltage with the comparator threshold voltage. The switch is configured to discharge the capacitor based on the comparison. The clock generator logic is configured to generate a clock signal based on the comparison, such that a frequency of the clock signal is a function of the ratio and is independent of the current and the comparator threshold voltage.

摘要翻译： 本公开的方面提供电路。 电路包括电流发生器，电容器，比较器，开关和时钟发生器逻辑。 电流发生器被配置为产生与比较器阈值电压成正比的电流。 电容器被配置为由电流充电以具有电容器电压。 比较器配置为将电容器电压与比较器阈值电压进行比较。 开关被配置为基于比较来放电电容器。 时钟发生器逻辑被配置为基于比较产生时钟信号，使得时钟信号的频率是该比率的函数，并且与电流和比较器阈值电压无关。