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1.发明授权Variable-gain multistage amplifier with broad bandwidth and reduced phase variations 有权可变增益多级放大器，带宽宽，相位变化减小公开(公告)号：US06246289B1
公开(公告)日：2001-06-12
申请号：US09507562
申请日：2000-02-18
IPC分类号： H03F345
CPC分类号： H03G1/0023
摘要： A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors. The amplifier further includes two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.
摘要翻译： 一种具有宽带宽和相位变化较小的可编程增益多级放大器，具有由第一电流源偏置的差分输入级，馈送差分电压信号，该级连接到阴极端子连接的一对二极管 到由双极晶体管的集电极端子提供的由第二电流源偏置并且其中集电极端子连接到负载电阻器的各个双极晶体管，放大器的差分输出被提供。 放大器还包括两个电路分支，每个电路分支由双极晶体管和第三电流源构成，第三电流源分别连接到双极晶体管的集电极端子和发射极端子，其中基极端子接收差分电压信号 并且集电极端子连接到两个二极管中的相应一个的阴极端子，电路分支通过一对电容器相互连接。
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2.发明授权Amplifier with programmable gain and input linearity usable in high-frequency lines 有权具有可编程增益和输入线性度的放大器可用于高频线路
公开(公告)号：US6037838A
公开(公告)日：2000-03-14
申请号：US264296
申请日：1999-03-08
CPC分类号： H03G7/06 , H03G1/0023
摘要： An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.
摘要翻译： 在高频下具有可编程增益和输入线性度的放大器可以增加增益，而不会影响输入线性度并且不会显着增加电流消耗。 放大器包括输入级，其接收用于通过压缩执行其电流转换的电压信号。 输出级连接到输入级，并且解压缩由输入级提供的信号，以产生其增益放大。 放大器还包括插入在输入级和输出级之间的至少一个电流放大器级。 至少一个电流放大器包括串联连接到负载二极管和电流源的至少一个双极晶体管。 在所述至少一个放大器级中提供所述负载二极管的跨导的减小以确定所述放大器的可编程增益因子。
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公开(公告)号：US06523057B1
公开(公告)日：2003-02-18
申请号：US09307083
申请日：1999-05-07
IPC分类号： G06F750
CPC分类号： G06F7/5095 , G06F2207/3884
摘要： A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at least one second stage having incrementer/decrementer means for performing an increment, decrement or identity operation on a most significant part of the output of the accumulator. The incrementer/decrementer means includes logic means for triggering the increment, a decrement or identity operation on the most significant part of the accumulator output based on a decision made on results obtained at the previous clock period.
摘要翻译： 高速，宽动态范围的数字累加器包括第一加法器级，其中从前一时钟周期将输入加法相加到累加器的输出的最低有效部分的值。 累加器还包括至少一个第二级，其具有递增器/减法器装置，用于在累加器的输出的最重要部分上执行增量，减量或标识操作。 加法器/递减器装置包括用于基于对在先前时钟周期获得的结果的决定来触发增量的触发增量，累加器输出的最高有效部分的递减或识别操作的逻辑装置。
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公开(公告)号：US06271688B1
公开(公告)日：2001-08-07
申请号：US09596510
申请日：2000-06-19
IPC分类号： H03K522
CPC分类号： H03F3/45197 , H03F2203/45466 , H03F2203/45494
摘要： A transconductor includes a differential stage formed by a pair of input transistors, and a resistive line of degeneration connecting the sources of the input transistors. A bias current generator is coupled between the source of each input transistor and ground. The resistive line of degeneration is formed by one or more transistors connected in series, the gates of which are coupled to a voltage reference. The voltage reference is at least equal to the common mode voltage of the differential stage. The one or more transistors forming the resistive line of degeneration are sized to operate in the triode region.
摘要翻译： 跨导体包括由一对输入晶体管形成的差分级和连接输入晶体管的源极的退化电阻线。 偏置电流发生器耦合在每个输入晶体管的源极和地之间。 退化的电阻线由串联连接的一个或多个晶体管形成，其栅极耦合到电压基准。 电压基准至少等于差动级的共模电压。 形成退化电阻线的一个或多个晶体管的尺寸被设计成在三极管区域中工作。
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5.发明授权公开(公告)号：US06369741B1
公开(公告)日：2002-04-09
申请号：US09611695
申请日：2000-07-07
IPC分类号： H03M112
CPC分类号： G11B20/10481 , G11B20/10009 , G11B20/10037
摘要： A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.
摘要翻译： 提供了一种用于定义用于磁性介质大容量存储器件的读取通道的预均衡的低通滤波器的升压和截止频率参数的编程值的方法，以确保最终的自适应滤波器的最佳功能条件 均衡 该方法包括预编程用于每个磁介质的预均衡低通滤波器的升压和截止频率参数的瞬时数字值，作为实现确定性的自适应滤波器的有意识的瞬时操作参数的函数 在磁性介质的修剪扫描期间信号的均衡。
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6.发明授权
公开(公告)号：US5805492A
公开(公告)日：1998-09-08
申请号：US722572
申请日：1996-09-27
申请人： Danilo Gerna , Marco Pasotti , Stefano Marchese
发明人： Danilo Gerna , Marco Pasotti , Stefano Marchese
CPC分类号： G11C27/00 , G11C27/024
摘要： The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.
摘要翻译： 用于存储光学图像作为电荷的电容单元RAAM的速度通过对两行或两行预采样电容器的串行模拟输入信号进行预取样来大大增强，每个或两行预采样电容器由相同数量的电容器组成， 电容单元RAAM，并通过所述存储器的所选行以并行模式“写入”。 存储在所述两个预采样行中的一个的电容器中的值被传送（写入）到存储器的选定行的相应单元中，同时在另一行预采样电容器上继续进行预采样。
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