公开(公告)号：US08989331B2

公开(公告)日：2015-03-24

申请号：US11806397

申请日：2007-05-31

申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

IPC分类号： H04L7/00 ,  H04L7/02 ,  G06F1/12

CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

公开(公告)号：US20070280396A1

公开(公告)日：2007-12-06

申请号：US11806397

申请日：2007-05-31

申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

IPC分类号： H04L7/00

CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

公开(公告)号：US06263195B1

公开(公告)日：2001-07-17

申请号：US09249904

申请日：1999-02-12

申请人： Edward L. Niu ,  Sam H. Liu ,  Gregory S. Caso

发明人： Edward L. Niu ,  Sam H. Liu ,  Gregory S. Caso

IPC分类号： H03K900

CPC分类号： H04B1/28 ,  H04B1/00

摘要： A wideband digital tuner (14′) has an analog front-end section (10), a high speed analog-to-digital converter (12), demultiplexer (13) and a plurality of filters (341-342) arranged in a parallel input architecture to process wideband digital data received at extremely high sampling rates, such as at 2 Gsps (giga-samples per second). The tuner greatly attenuates an undesired spectral half of the wide bandwidth digital spectrum of the incoming digital signal using a complex band-pass filter, such as a Hilbert Transform filter. The tuner places the remaining half of the wide bandwidth digital spectrum of the incoming digital signal at complex baseband and down samples by 2. The architecture of the tuner can be partitioned into two separate halves which are hardware copies of each other.

摘要翻译： 宽带数字调谐器（14'）具有模拟前端部分（10），高速模数转换器（12），解复用器（13）和并联布置的多个滤波器（341-342） 输入架构来处理以非常高的采样率接收的宽带数字数据，例如2 Gsps（千兆比特每秒）。 调谐器使用诸如希尔伯特变换滤波器的复带通滤波器大大地衰减输入数字信号的宽带数字频谱的不希望的频谱一半。 调谐器将输入数字信号的宽带数字频谱的剩余一半放置在复杂的基带和下采样中。调谐器的架构可以分为两个分开的两个，这两个是相互的硬件副本。

公开(公告)号：US06259314B1

公开(公告)日：2001-07-10

申请号：US09249908

申请日：1999-02-12

申请人： Sam H. Liu ,  Edward L. Niu ,  Vincent C. Moretti

发明人： Sam H. Liu ,  Edward L. Niu ,  Vincent C. Moretti

IPC分类号： H04B1700

CPC分类号： H04L1/24

摘要： The invention is a demodulator (50, 100) and a method of data reception and testing of a demodulator. A demodulator in accordance with the invention includes an input signal source (52, 102) having an output which during data reception is a data signal and which during testing of the demodulator is a reference signal; a tuner (54, 101) having a tuner input coupled to the output of the input signal source and a tuner output, the tuner including a frequency converter (20, 36) which frequency shifts the data signal to a lower carrier frequency during data reception to cause the tuner to output at the tuner output the lower carrier frequency modulated with the data signal and which upwardly frequency shifts the reference signal to a test carrier frequency during the testing; and a test data source (56, 105) which applies a test data signal to the tuner during the testing to cause the tuner to output at the tuner output the test carrier frequency modulated with the test data signal.

摘要翻译： 本发明是解调器（50,100）以及解调器的数据接收和测试方法。 根据本发明的解调器包括输入信号源（52,102），其具有在数据接收期间是数据信号的输出，并且在解调器的测试期间是参考信号; 具有耦合到输入信号源的输出的调谐器输入和调谐器输出的调谐器（54,101），所述调谐器包括频率转换器（20,36），其在数据接收期间将数据信号频移到较低的载波频率 使调谐器在调谐器输出端输出用数据信号调制的较低载波频率，并且在测试期间向上频率地将参考信号移位到测试载波频率; 以及测试数据源（56,105），其在测试期间将测试数据信号施加到调谐器，以使得调谐器在调谐器输出输出由测试数据信号调制的测试载波频率。