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    Method and system for advance high performance bus synchronizer
    1.
    发明授权
    Method and system for advance high performance bus synchronizer 有权
    先进高性能总线同步器的方法和系统

    公开(公告)号：US08989331B2

    公开(公告)日：2015-03-24

    申请号：US11806397

    申请日：2007-05-31

    申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

    发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

    IPC分类号： H04L7/00 ,  H04L7/02 ,  G06F1/12

    CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

    摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

    摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

    Method and system for advance high performance bus synchronizer
    2.
    发明申请
    Method and system for advance high performance bus synchronizer 有权
    先进高性能总线同步器的方法和系统

    公开(公告)号：US20070280396A1

    公开(公告)日：2007-12-06

    申请号：US11806397

    申请日：2007-05-31

    申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

    发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

    摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

    摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

    CONFIGURABLE MEMORY CONTROLLER
    5.
    发明申请
    CONFIGURABLE MEMORY CONTROLLER 审中-公开
    可配置内存控制器

    公开(公告)号：US20110276766A1

    公开(公告)日：2011-11-10

    申请号：US12774462

    申请日：2010-05-05

    申请人： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty ,  Lance Flake ,  Vinay Bhasin

    发明人： Mark N. Fullerton ,  Sathish Kumar Radhakrishnan ,  Brent Mulholland ,  Ravi S. Setty ,  Lance Flake ,  Vinay Bhasin

    IPC分类号： G06F12/00

    CPC分类号： G06F1/3275 ,  G06F1/3206 ,  G06F1/3215 ,  G06F13/1626 ,  H04W52/0274 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D70/142 ,  Y02D70/144

    摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

    摘要翻译： 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。