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    METHOD AND SYSTEM FOR PROCESSING AUDIO SIGNALS IN A CENTRAL AUDIO HUB
    1.
    发明申请
    METHOD AND SYSTEM FOR PROCESSING AUDIO SIGNALS IN A CENTRAL AUDIO HUB 审中-公开
    在中央音频总线处理音频信号的方法和系统

    公开(公告)号：US20120250877A1

    公开(公告)日：2012-10-04

    申请号：US13077458

    申请日：2011-03-31

    申请人： Taiyi Cheng ,  Hongwei Kong ,  Nelson Sollenberger ,  Mark Fullerton ,  Chin Sieh Lee ,  Timothy Pong ,  Yafang Feng ,  Claire Marie Suzanne Simeon ,  Michael Liu ,  Kenneth Ma ,  Chaoyang Zhao

    发明人： Taiyi Cheng ,  Hongwei Kong ,  Nelson Sollenberger ,  Mark Fullerton ,  Chin Sieh Lee ,  Timothy Pong ,  Yafang Feng ,  Claire Marie Suzanne Simeon ,  Michael Liu ,  Kenneth Ma ,  Chaoyang Zhao

    IPC分类号： H04B3/00

    CPC分类号： G06F3/165

    摘要： A central audio hub, comprising an audio switch, a bus matrix, and an audio buffer, is triggered to read audio samples of an audio stream from the audio buffer. The central audio hub routes the audio samples via the bus matrix to one or more surrounding audio modules such as an audio codec and an audio interface communicatively coupled to the central audio hub. The audio stream may be directly from an external application processor or from an external DDR. With the audio stream from the DDR, a DMA controller may fetch the audio samples from the DDR in response to a request received from the audio buffer, and store the fetched audio samples into the audio buffer for routing. The audio switch may be triggered at a determined sampling rate to read the audio samples from the audio buffer utilizing a determined sample format, and to route the audio samples to the surrounding audio modules.

    摘要翻译： 触发包括音频开关，总线矩阵和音频缓冲器的中央音频集线器，从音频缓冲器读取音频流的音频样本。 中央音频集线器将音频样本经由总线矩阵路由到一个或多个周围的音频模块，例如通信地耦合到中央音频集线器的音频编解码器和音频接口。 音频流可以直接来自外部应用处理器或外部DDR。 利用来自DDR的音频流，DMA控制器可以响应于从音频缓冲器接收到的请求，从DDR获取音频样本，并将获取的音频样本存储到音频缓冲器中进行路由。 可以以确定的采样速率触发音频开关，以利用确定的采样格式从音频缓冲器读取音频样本，并将音频样本路由到周围的音频模块。

    Method and system for advance high performance bus synchronizer
    2.
    发明申请
    Method and system for advance high performance bus synchronizer 有权
    先进高性能总线同步器的方法和系统

    公开(公告)号：US20070280396A1

    公开(公告)日：2007-12-06

    申请号：US11806397

    申请日：2007-05-31

    申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

    发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar ,  Vafa J. Rakshani

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

    摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

    摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

    Method and system for advance high performance bus synchronizer
    4.
    发明授权
    Method and system for advance high performance bus synchronizer 有权
    先进高性能总线同步器的方法和系统

    公开(公告)号：US08989331B2

    公开(公告)日：2015-03-24

    申请号：US11806397

    申请日：2007-05-31

    申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

    发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

    IPC分类号： H04L7/00 ,  H04L7/02 ,  G06F1/12

    CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

    摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

    摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。