公开(公告)号：US20240168913A1

公开(公告)日：2024-05-23

申请号：US18518695

申请日：2023-11-24

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06F15/78 ,  G06F16/901 ,  G06F17/16

CPC classification number: G06F15/7885 ,  G06F15/7839 ,  G06F16/9024 ,  G06F17/16

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

公开(公告)号：US20240378147A1

公开(公告)日：2024-11-14

申请号：US18144819

申请日：2023-05-08

Applicant: SambaNova Systems, Inc.

Inventor： Mark William Gottscho ,  Ram SIVARAMAKRISHNAN ,  David Brian JACKSON ,  Ruddhi CHAPHEKAR ,  Tuowen Zhao ,  Lei Xia

IPC: G06F12/06 ,  G06F7/544

Abstract: A convolution calculation engine includes a kernel element counter for a convolution operation between a kernel and an input tensor. The kernel element counter wraps back to an initial kernel count value after reaching a maximum kernel count value. The convolution calculation engine also includes an offset look-up table (LUT) that provides a relative input offset into the input tensor based on an output of the kernel element counter and input location calculation logic that provides an input location within an input tensor for the convolution operation based on the relative input offset provided by the offset LUT.

公开(公告)号：US20220309316A1

公开(公告)日：2022-09-29

申请号：US17364110

申请日：2021-06-30

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.

公开(公告)号：US20220309325A1

公开(公告)日：2022-09-29

申请号：US17713157

申请日：2022-04-04

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.

公开(公告)号：US20220309324A1

公开(公告)日：2022-09-29

申请号：US17700452

申请日：2022-03-21

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: A processing graph of an application with a sequence of processing nodes is obtained which processes an input and generates an intermediate representation a further intermediate representation, and an output representation of the input at stages in the sequence of processing nodes. Graph metadata is generated that specifies a non-overlapping target tiling configuration for the output representation, an overlapping tiling configuration for the input, an overlapping tiling configuration for the intermediate representation, and a third tiling configuration for the further intermediate representation. The processing graph is modified based on the graph metadata to conform to the parameters specified by the graph metadata. A set of computer instructions is then created to execute the modified processing graph on a target processing system.

公开(公告)号：US20220309028A1

公开(公告)日：2022-09-29

申请号：US17384515

申请日：2021-07-23

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06F15/78 ,  G06F17/16 ,  G06F16/901

Abstract: Disclosed is a data processing system that includes a plurality of reconfigurable processors and processor memory. Runtime logic, operatively coupled to the plurality of reconfigurable processors and the processor memory, is configured to configure at least one reconfigurable processor in the plurality of reconfigurable processors with a first subgraph in a sequence of subgraphs of a graph; load an input onto the processor memory; on a tile-by-tile basis, process a first set of input tiles from the input through the first subgraph and generate a first set of intermediate tiles, load the first set of intermediate tiles onto the processor memory, and process the first set of intermediate tiles through the first subgraph and generate a first set of output tiles; and compose output tiles in the first set of output tiles into a first composed input, and load the first composed input onto the processor memory.

公开(公告)号：US20240378259A1

公开(公告)日：2024-11-14

申请号：US18144818

申请日：2023-05-08

Applicant: SambaNova Systems, Inc.

Inventor： Mark William Gottscho ,  Ram SIVARAMAKRISHNAN ,  David Brian JACKSON ,  Ruddhi CHAPHEKAR ,  Tuowen Zhao ,  Lei Xia

IPC: G06F17/15 ,  G06F7/544

Abstract: A convolution calculation engine to perform a convolution operation includes a convolution address compute unit. The convolution address compute unit includes an outer output base location register to provide an outer output base location for the convolution operation and an outer input base location register to provide an outer input base location for the convolution operation. It also includes a kernel element counter that starts to count from an initial kernel count value to a maximum kernel count value in response to a change in the outer output base location and a kernel offset generator to generate a kernel offset based on an output of the kernel element counter. In addition, the convolution address compute unit includes inner location logic to calculate an output location based on the outer output base location and an input location based on the outer input base location and output of the kernel element counter.

公开(公告)号：US20230325163A1

公开(公告)日：2023-10-12

申请号：US18206829

申请日：2023-06-07

Applicant: SambaNova Systems, Inc.

Inventor： Weiwei CHEN ,  Raghu PRABHAKAR ,  David Alan KOEPLINGER ,  Sitanshu GUPTA ,  Ruddhi CHAPHEKAR ,  Ajit PUNJ ,  Sumti JAIRATH

IPC: G06F8/41 ,  G06F15/78

CPC classification number: G06F8/452 ,  G06F15/7867 ,  G06F8/41 ,  G06F15/825

Abstract: The technology disclosed relates to storing a dataflow graph with a plurality of compute nodes that transmit data along data connections, and controlling data transmission between compute nodes in the plurality of compute nodes along the data connections by using control connections to control writing of data.

公开(公告)号：US20220309317A1

公开(公告)日：2022-09-29

申请号：US17364129

申请日：2021-06-30

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

公开(公告)号：US20220309323A1

公开(公告)日：2022-09-29

申请号：US17700336

申请日：2022-03-21

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: A data processing system includes memory and reconfigurable processors, operatively coupled to the memory, configured to execute a sequence of subgraphs of a graph. The sequence of subgraphs includes a preceding subgraph and a succeeding subgraph. The data processing system also includes data flow logic, operatively coupled to the reconfigurable processors and the memory, configured to store a tiled output of the preceding subgraph as a composed input in the memory and make available parts of the composed input for processing by the succeeding subgraph.