公开(公告)号：US20100032757A1

公开(公告)日：2010-02-11

申请号：US12537329

申请日：2009-08-07

申请人： Sameer P. PENDHARKAR

发明人： Sameer P. PENDHARKAR

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L21/823425

摘要： A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.

摘要翻译： 一种三端双向横向扩散金属氧化物半导体（LDMOS）晶体管，其包括两个单向LDMOS晶体管，其串联共享共用漏极节点，并且被配置为使得单向LDMOS晶体管的源节点用作源极和漏极端子 的双向LDMOS晶体管。 源极短路到每个LDMOS晶体管的背栅。 每个LDMOS晶体管的栅极节点被钳位到其相应的源极节点以防止源极栅极击穿，并且双向LDMOS晶体管的栅极端子通过阻塞二极管连接到组成的单向LDMOS晶体管的栅极节点。 普通漏极是一个深n阱，将两个p型背栅区隔离开来。 栅极节点钳位可以是一对背对背齐纳二极管或一对串联的源极到源极的自偏压MOS晶体管。

公开(公告)号：US20110180842A1

公开(公告)日：2011-07-28

申请号：US12694872

申请日：2010-01-27

申请人： Sameer P. PENDHARKAR

发明人： Sameer P. PENDHARKAR

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L21/761

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/749

摘要： An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MOS gate between the centralized drain diffused region and a source diffused region is shorted to the source diffused region. A process of forming the integrated circuit having the SCRMOS transistor is also disclosed.

摘要翻译： 包含SCRMOS晶体管的集成电路。 SCRMOS晶体管具有一个漏极结构，具有集中的漏极扩散区域和分布式SCR端子，以及具有分布式漏极扩散区域和SCR端子的第二漏极结构。 集中式漏极扩散区域和源极扩散区域之间的MOS栅极与源极扩散区域短路。 还公开了形成具有SCRMOS晶体管的集成电路的工艺。

公开(公告)号：US20100032794A1

公开(公告)日：2010-02-11

申请号：US12537318

申请日：2009-08-07

申请人： Sameer P. PENDHARKAR ,  Binghua HU

发明人： Sameer P. PENDHARKAR ,  Binghua HU

IPC分类号： H01L29/861 ,  H01L21/02

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/66136

摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

摘要翻译： 公开了一种高压二极管，其中n型阴极由未接触的重掺杂n型环包围以将注入的孔反射回阴极区域进行复合或收集。 重掺杂n型环中的掺杂剂密度优选为阴极中掺杂剂密度的100至10,000倍。 重掺杂的n型区通常连接到阴极下方的n型掩埋层。 重掺杂的n型环优选地从阴极触点定位至少一个孔扩散长度。 所公开的高电压二极管可以集成到集成电路中，而不需要添加工艺步骤。

公开(公告)号：US20120164814A1

公开(公告)日：2012-06-28

申请号：US13409689

申请日：2012-03-01

申请人： Sameer P. PENDHARKAR ,  Binghua HU

发明人： Sameer P. PENDHARKAR ,  Binghua HU

IPC分类号： H01L21/76

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/66136

摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

摘要翻译： 公开了一种高压二极管，其中n型阴极由未接触的重掺杂n型环包围以将注入的孔反射回阴极区域进行复合或收集。 重掺杂n型环中的掺杂剂密度优选为阴极中掺杂剂密度的100至10,000倍。 重掺杂的n型区通常连接到阴极下方的n型掩埋层。 重掺杂的n型环优选地从阴极触点定位至少一个孔扩散长度。 所公开的高电压二极管可以集成到集成电路中，而不需要添加工艺步骤。

公开(公告)号：US20110180870A1

公开(公告)日：2011-07-28

申请号：US12694808

申请日：2010-01-27

申请人： Sameer P. PENDHARKAR

发明人： Sameer P. PENDHARKAR

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/66393 ,  H01L27/0262 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/402 ,  H01L29/456 ,  H01L29/7436 ,  H01L29/749

摘要： An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region. An SCRMOS transistor with a RESURF region around the drain region and SCR terminal. A process of forming an integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal.

摘要翻译： 具有SCRMOS晶体管的集成电路，其具有围绕漏极区域和SCR端子的RESURF区域。 RESURF区域是与漂移区域相同的导电类型，并且比漂移区域更重掺杂。 一个SCRMOS晶体管，在漏极区域和SCR端子周围具有RESURF区域。 形成具有SCRMOS晶体管的集成电路的工艺，其具有围绕漏极区域和SCR端子的RESURF区域。

公开(公告)号：US20100032756A1

公开(公告)日：2010-02-11

申请号：US12537326

申请日：2009-08-07

申请人： Sameer P. PENDHARKAR ,  Binghua HU ,  Xinfen CHEN

发明人： Sameer P. PENDHARKAR ,  Binghua HU ,  Xinfen CHEN

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/73 ,  H01L27/092 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/823892 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7322 ,  H01L29/7816 ,  H01L29/7833

摘要： A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

摘要翻译： 公开了一种掩埋层结构，其包括与连接到IC中的组件的相同导电类型的深阱连接的高电压埋层相邻的浮置掩埋层结构。 浮置掩埋层结构围绕高压掩埋层并且延伸埋层的耗尽区以减小掩埋层的侧边缘处的峰值电场。 当浮动掩埋层结构的尺寸和间距被优化时，连接到掩埋层的阱可被偏压到100伏而不会破坏。 添加围绕第一浮动掩埋层结构的第二浮动掩埋层结构允许埋入层的操作高达140伏。 具有浮动掩埋层结构的掩埋层结构可以并入DEPMOS晶体管，LDMOS晶体管，埋地集电极npn双极晶体管和隔离CMOS电路中。