Stacked ESD clamp with reduced variation in clamp voltage
    1.
    发明授权
    Stacked ESD clamp with reduced variation in clamp voltage 有权
    堆叠的ESD钳位钳位电压变化较小

    公开(公告)号:US08598008B2

    公开(公告)日:2013-12-03

    申请号:US13277939

    申请日:2011-10-20

    IPC分类号: H01L21/331 H01L21/8222

    摘要: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

    摘要翻译: 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法,该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。

    STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE
    2.
    发明申请
    STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE 有权
    堆积电压降低变化的堆积ESD钳位

    公开(公告)号:US20120098098A1

    公开(公告)日:2012-04-26

    申请号:US13277939

    申请日:2011-10-20

    IPC分类号: H01L27/082 H01L21/8222

    摘要: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

    摘要翻译: 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法,该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。