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公开(公告)号：US08790981B2
公开(公告)日：2014-07-29
申请号：US12536200
申请日：2009-08-05
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/105 , H01L29/456 , H01L29/66659
摘要： A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.
摘要翻译： 公开了一种功率场效应晶体管（FET），其以少至六个光刻步骤制造，并且能够以高电压漏极电位（例如，高达约50伏特）切换电流。 在所描述的n沟道金属氧化物半导体（NMOS）实施例中，漏极节点包括具有浅结梯度的n阱区，使得n阱和衬底之间的耗尽区宽于1微米。 使用毯式离子注入避免阈值调节和轻掺杂漏极（LDD）种植体的额外光刻步骤。 修改的实施例提供部分在栅极下方的LDD区域的延长以延长使用寿命。
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公开(公告)号：US08264038B2
公开(公告)日：2012-09-11
申请号：US12537326
申请日：2009-08-07
申请人： Sameer P. Pendharkar , Binghua Hu , Xinfen Chen
发明人： Sameer P. Pendharkar , Binghua Hu , Xinfen Chen
IPC分类号： H01L29/06 , H01L29/78 , H01L29/73 , H01L27/092 , H01L21/761
CPC分类号： H01L21/761 , H01L21/823892 , H01L29/0623 , H01L29/0653 , H01L29/086 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7322 , H01L29/7816 , H01L29/7833
摘要： A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.
摘要翻译： 公开了一种掩埋层结构，其包括与连接到IC中的组件的相同导电类型的深阱连接的高电压埋层相邻的浮置掩埋层结构。 浮置掩埋层结构围绕高压掩埋层并且延伸埋层的耗尽区以减小掩埋层的侧边缘处的峰值电场。 当浮动掩埋层结构的尺寸和间距被优化时，连接到掩埋层的阱可被偏压到100伏而不会破坏。 添加围绕第一浮动掩埋层结构的第二浮动掩埋层结构允许埋入层的操作高达140伏。 具有浮动掩埋层结构的掩埋层结构可以并入DEPMOS晶体管，LDMOS晶体管，埋地集电极npn双极晶体管和隔离CMOS电路中。
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公开(公告)号：US08217453B2
公开(公告)日：2012-07-10
申请号：US12537329
申请日：2009-08-07
申请人： Sameer P. Pendharkar
发明人： Sameer P. Pendharkar
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L21/823425
摘要： A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.
摘要翻译： 一种三端双向横向扩散金属氧化物半导体（LDMOS）晶体管，其包括两个单向LDMOS晶体管，其串联共享共用漏极节点，并且被配置为使得单向LDMOS晶体管的源节点用作源极和漏极端子 的双向LDMOS晶体管。 源极短路到每个LDMOS晶体管的背栅。 每个LDMOS晶体管的栅极节点被钳位到其相应的源极节点以防止源极栅极击穿，并且双向LDMOS晶体管的栅极端子通过阻塞二极管连接到组成的单向LDMOS晶体管的栅极节点。 普通漏极是一个深n阱，将两个p型背栅区隔离开来。 栅极节点钳位可以是一对背对背齐纳二极管或一对串联的源极到源极的自偏压MOS晶体管。
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公开(公告)号：US20120098098A1
公开(公告)日：2012-04-26
申请号：US13277939
申请日：2011-10-20
IPC分类号： H01L27/082 , H01L21/8222
CPC分类号： H01L27/082 , H01L21/8222 , H01L27/0259 , H01L27/0823 , H01L29/735
摘要： An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
摘要翻译： 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。
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公开(公告)号：US08120108B2
公开(公告)日：2012-02-21
申请号：US12694808
申请日：2010-01-27
申请人： Sameer P. Pendharkar
发明人： Sameer P. Pendharkar
IPC分类号： H01L29/66
CPC分类号： H01L29/66393 , H01L27/0262 , H01L29/063 , H01L29/0649 , H01L29/0692 , H01L29/0834 , H01L29/1016 , H01L29/402 , H01L29/456 , H01L29/7436 , H01L29/749
摘要： An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region. An SCRMOS transistor with a RESURF region around the drain region and SCR terminal. A process of forming an integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal.
摘要翻译： 具有SCRMOS晶体管的集成电路，其具有围绕漏极区域和SCR端子的RESURF区域。 RESURF区域是与漂移区域相同的导电类型，并且比漂移区域更重掺杂。 一个SCRMOS晶体管，在漏极区域和SCR端子周围具有RESURF区域。 形成具有SCRMOS晶体管的集成电路的工艺，其具有围绕漏极区域和SCR端子的RESURF区域。
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公开(公告)号：US20110073955A1
公开(公告)日：2011-03-31
申请号：US12962159
申请日：2010-12-07
IPC分类号： H01L27/06
CPC分类号： H01L21/8249 , H01L21/76232 , H01L27/0623
摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.
摘要翻译： 一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。 绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。
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公开(公告)号：US20100032774A1
公开(公告)日：2010-02-11
申请号：US12536200
申请日：2009-08-05
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/105 , H01L29/456 , H01L29/66659
摘要： A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.
摘要翻译： 公开了一种功率场效应晶体管（FET），其以少至六个光刻步骤制造，并且能够以高电压漏极电位（例如，高达约50伏特）切换电流。 在所描述的n沟道金属氧化物半导体（NMOS）实施例中，漏极节点包括具有浅结梯度的n阱区，使得n阱和衬底之间的耗尽区宽于1微米。 使用毯式离子注入避免阈值调节和轻掺杂漏极（LDD）种植体的额外光刻步骤。 修改的实施例提供部分在栅极下方的LDD区域的延长以延长使用寿命。
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公开(公告)号：US20100032757A1
公开(公告)日：2010-02-11
申请号：US12537329
申请日：2009-08-07
申请人： Sameer P. PENDHARKAR
发明人： Sameer P. PENDHARKAR
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L21/823425
摘要： A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.
摘要翻译： 一种三端双向横向扩散金属氧化物半导体（LDMOS）晶体管，其包括两个单向LDMOS晶体管，其串联共享共用漏极节点，并且被配置为使得单向LDMOS晶体管的源节点用作源极和漏极端子 的双向LDMOS晶体管。 源极短路到每个LDMOS晶体管的背栅。 每个LDMOS晶体管的栅极节点被钳位到其相应的源极节点以防止源极栅极击穿，并且双向LDMOS晶体管的栅极端子通过阻塞二极管连接到组成的单向LDMOS晶体管的栅极节点。 普通漏极是一个深n阱，将两个p型背栅区隔离开来。 栅极节点钳位可以是一对背对背齐纳二极管或一对串联的源极到源极的自偏压MOS晶体管。
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公开(公告)号：US20080293206A1
公开(公告)日：2008-11-27
申请号：US11753789
申请日：2007-05-25
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.
摘要翻译： 示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。 具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。 可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。 多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约90或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。 在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。
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公开(公告)号：US06797547B2
公开(公告)日：2004-09-28
申请号：US10679220
申请日：2003-10-03
IPC分类号： H01L2100
CPC分类号： H01L29/66681 , H01L29/0657 , H01L29/4175 , H01L29/66674 , H01L29/66772 , H01L29/7824 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.
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