Abstract:
A display device includes a substrate; an active pattern disposed on the substrate; a first insulating layer; a first conductive layer disposed on the first insulating layer and having a driving gate electrode; a second insulating layer; a second conductive layer disposed on the second insulating layer and having a first storage electrode; a third insulating layer; a third conductive layer disposed on the third insulating layer and having a second storage electrode; and a light-emitting element disposed on the third conductive layer, wherein the second storage electrode overlaps the first storage electrode via the third insulating layer to form a first capacitor, the first storage electrode overlaps the driving gate electrode via the second insulating layer to form a second capacitor, and the driving gate electrode, the first storage electrode, and the second storage electrode at least partially overlap each other.
Abstract:
A scan driver includes two or more scan signal output circuits (SSOC), each being coupled to a first scan line (FSL) and a second scan line (SSL), and including a driving circuit, a first buffer circuit (FBC), and a second buffer circuit (SBC). The driving circuit applies a first driving signal (DS) to a first driving node (DN) and applies a second DS to a second DN based on an input signal, a clock signal (CS), a display-on signal, and an on-level voltage. The input signal is a scan start signal or a previous scan signal. The FBC outputs a sensing signal to the SSL based on the first DS, the second DS, an off-level voltage, and a sensing CS. The SBC outputs a scan signal to the FSL based on the first DS, the second DS, the off-level voltage, and a scan CS.
Abstract:
The present invention relates to a liquid crystal display including: a lower electrode including a unit pixel electrode; an upper electrode including an upper unit electrode facing the unit pixel electrode; and a liquid crystal layer between the lower electrode and the upper electrode and including a plurality of liquid crystal molecules aligned approximately perpendicular to the surfaces of the lower electrode and the upper electrode in the absence of an electric field, wherein the unit pixel electrode includes a stem forming a boundary between a plurality of sub-regions and a plurality of minute branches extending in different directions in two different sub-regions, the upper unit electrode includes an opening facing the stem and extending parallel to the stem, any alignment aid to pretilt the liquid crystal molecules is absent, and a length of the minute branches is equal to or less than about 53 μm.
Abstract:
A display device is provided that includes a first substrate, a gate wiring formed on the first substrate and extending in a first direction, a data wiring insulated from and crossing the gate wiring and extending in a second direction, and a pixel electrode including a first subpixel electrode to which a first data voltage is applied from the data wiring and a second subpixel electrode to which a second data voltage different from the first data voltage is applied from the data wiring, wherein the first subpixel electrode is surrounded by the second subpixel electrode, and the second subpixel electrode includes a plurality of slit patterns formed in portions thereof which are adjacent to the first subpixel electrode.
Abstract:
A display device includes: a gate line transmitting a gate line; a data line transmitting a data voltage; a first switching element and a second switching element connected to the gate line and the data line; a third switching element connected between the second switching element and a terminal providing a first reference voltage signal; a first liquid crystal capacitor connected to the first switching element; and a second liquid crystal capacitor connected to the second switching element, wherein the third switching element includes a first control terminal connected to the gate line and a second control terminal connected to a terminal providing a second reference voltage signal. The second and third switching elements are operated to form a voltage dividing network having a respective voltage dividing ratio.
Abstract:
A display device includes connection lines, pulse amplitude modulation (PAM) data lines configured to receive pulse width modulation (PWM) data voltages, PWM data lines configured to receive the PWM data voltages, a first connection control line configured to receive a first connection control signal, a second connection control line configured to receive a second connection control signal, subpixels connected to the PWM data lines and the PAM data lines, and a first demultiplexer (demux) unit configured to connect the connection lines to the PAM data lines or to the PWM data lines according to the first connection control signal and the second connection control signal.
Abstract:
A display device includes a substrate; an active pattern disposed on the substrate; a first insulating layer; a first conductive layer disposed on the first insulating layer and having a driving gate electrode; a second insulating layer; a second conductive layer disposed on the second insulating layer and having a first storage electrode; a third insulating layer; a third conductive layer disposed on the third insulating layer and having a second storage electrode; and a light-emitting element disposed on the third conductive layer, wherein the second storage electrode overlaps the first storage electrode via the third insulating layer to form a first capacitor, the first storage electrode overlaps the driving gate electrode via the second insulating layer to form a second capacitor, and the driving gate electrode, the first storage electrode, and the second storage electrode at least partially overlap each other.
Abstract:
An OLED display device includes a pixel having a switching transistor turned on by a scan signal received from a scan line and which transmits a data signal received from a data line to a first node, a driving transistor connected between the first node and a second node and through which a driving current corresponding to the data signal flows, a storage capacitor including one end connected to a power supply and another end connected to a gate electrode of the driving transistor, an OLED emitting light by the driving current, and a light emission control transistor connected between the second node and an anode of the OLED and which is turned on by an light emission control signal and transmits the driving current to the OLED. The switching transistor may be an n-type transistor, and the light emission control transistor is a p-type transistor.
Abstract:
A display device includes connection lines, pulse amplitude modulation (PAM) data lines configured to receive pulse width modulation (PWM) data voltages, PWM data lines configured to receive the PWM data voltages, a first connection control line configured to receive a first connection control signal, a second connection control line configured to receive a second connection control signal, subpixels connected to the PWM data lines and the PAM data lines, and a first demultiplexer (demux) unit configured to connect the connection lines to the PAM data lines or to the PWM data lines according to the first connection control signal and the second connection control signal.
Abstract:
A display device includes a first pixel driver connected to a sweep line, the first pixel driver generating a control current based on a first data voltage, a second pixel driver connected to a scan control line, the second pixel driver generating a driving current based on a second data voltage and controlling a period for which the driving current flows, based on the control current, and a light-emitting element connected to the second pixel driver to receive the driving current. The first pixel driver includes a first transistor generating the control current based on the first data voltage, a second transistor providing the first data voltage to a first electrode of the first transistor based on a scan write signal, and a first capacitor including a first capacitor electrode connected to a gate electrode of the first transistor, and a second capacitor electrode connected to the sweep line.