公开(公告)号：US20170343843A1

公开(公告)日：2017-11-30

申请号：US15483749

申请日：2017-04-10

Applicant: Samsung Display Co., Ltd

Inventor： Duk Sung KIM ,  Seung Hyun PARK ,  Jun Ho SONG ,  Sung Hoon LIM

IPC: G02F1/1368 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/134327 ,  G02F1/13439 ,  G02F1/136286 ,  G02F2001/136231 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2202/02 ,  G02F2202/10

Abstract: A liquid crystal display device comprising: a substrate; a gate line that is disposed on the substrate and extends in a first direction; a first insulating film that is disposed on the gate line; a semiconductor pattern that is disposed on the first insulating film; a first transparent electrode that is disposed on the semiconductor pattern, and has a first electrode and a second electrode being spaced apart from each other; a second insulating film that is disposed on the first transparent electrode and partially exposes the first electrode; a data line disposed on the second insulating film and extends in a second direction different from the first direction; a second transparent electrode that is disposed on the second insulating film and at least partially overlaps the second electrode; and a connecting electrode in direct contact with a portion of the exposed first electrode and the data line.

公开(公告)号：US20170192329A1

公开(公告)日：2017-07-06

申请号：US15395503

申请日：2016-12-30

Applicant: Samsung Display Co., Ltd.

Inventor： Dong Gun OH ,  Sung Hoon LIM ,  Do Hyun JUNG ,  Jean Ho SONG ,  Hyeon Jun LEE

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1345 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13456 ,  G02F2001/13629 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2202/02

Abstract: A display device may include a switching device, a gate line, a data line, a pixel electrode, and an auxiliary line. The switching device includes a first electrode, a second electrode, and a third electrode. The gate line is electrically connected to the first electrode. The data line crosses the gate line in a plan view of the display device and is electrically connected to the second electrode. The pixel electrode is electrically connected to the third electrode. The auxiliary line is electrically connected through the first gate line to the first electrode and crosses the gate line in the plan view of the display device.

公开(公告)号：US20230245612A1

公开(公告)日：2023-08-03

申请号：US18132704

申请日：2023-04-10

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G2310/08 ,  G09G2310/0267 ,  G09G2310/0275

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20230186849A1

公开(公告)日：2023-06-15

申请号：US17853129

申请日：2022-06-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yoon Jung CHAI ,  Won Jun LEE ,  Chol Ho KIM ,  Sung Hoon LIM ,  Yoo Seok JANG

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G3/2007

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

公开(公告)号：US20220254310A1

公开(公告)日：2022-08-11

申请号：US17728584

申请日：2022-04-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kang Nam KIM ,  You Mee HYUN ,  Beom Jun KIM ,  Jong Hwan LEE ,  Sung Hoon LIM ,  Duc Han CHO

IPC: G09G3/3266 ,  G09G3/20 ,  G11C19/28 ,  G09G3/36

Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

公开(公告)号：US20220005402A1

公开(公告)日：2022-01-06

申请号：US17478825

申请日：2021-09-17

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20200372851A1

公开(公告)日：2020-11-26

申请号：US16875682

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20240331608A1

公开(公告)日：2024-10-03

申请号：US18732585

申请日：2024-06-03

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam KIM ,  Sung Hoon LIM ,  Woo Geun LEE ,  Kyu Sik CHO ,  Jae Beom CHOI

IPC: G09G3/20 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/2092 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2310/0202 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US20230368733A1

公开(公告)日：2023-11-16

申请号：US18223459

申请日：2023-07-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yoon Jung CHAI ,  Won Jun LEE ,  Chol Ho KIM ,  Sung Hoon LIM ,  Yoo Seok JANG

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2310/0294 ,  G09G2320/0252 ,  G09G3/2007

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.