公开(公告)号：US10204935B2

公开(公告)日：2019-02-12

申请号：US15702797

申请日：2017-09-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Jin Cho ,  Joon-Hwa Bae ,  Byoung Kwon Choo ,  Byung Hoon Kang ,  Kwang Suk Kim ,  Woo Jin Cho ,  Jun Hyuk Cheon

IPC: H01L27/12 ,  B24B31/00 ,  C09G1/02 ,  H01L21/3105 ,  H01L21/66 ,  G09G3/3233 ,  H01L21/02 ,  H01L27/32 ,  H01L29/786

Abstract: A method for manufacturing a display device includes forming a first gate metal wire on a substrate, forming a first insulation layer that covers the first gate metal wire, forming a second gate metal wire on the first insulation layer, forming a second main insulation layer that covers the second gate metal wire, forming a second auxiliary insulation layer on the second main insulation layer, forming an exposed portion of an upper surface of the second main insulation layer by polishing the second auxiliary insulation layer, and forming a first data metal wire on the second main insulation layer and the second auxiliary insulation layer.

公开(公告)号：US10043860B2

公开(公告)日：2018-08-07

申请号：US15605431

申请日：2017-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Hoon Kang ,  Kwang Suk Kim ,  Joon-Hwa Bae ,  Woo Jin Cho ,  Hyun Jin Cho ,  Jun Hyuk Cheon ,  Byoung Kwon Choo

IPC: H01L29/08 ,  H01L27/32

Abstract: A method of manufacturing a display device includes: forming an active layer on a substrate; forming a first insulation layer covering the active layer; forming a gate metal line on the first insulation layer; forming a third insulation layer covering the gate metal line and including a silicon oxide; forming a fourth insulation layer including a silicon nitride on the third insulation layer; forming a fifth insulation layer including a silicon oxide on the fourth insulation layer; arranging a blocking member over a region in which the active layer and the gate metal line overlap; forming a fifth auxiliary insulation layer by doping nitrogen ions in the fifth insulation layer; and exposing a part of an upper surface of the fourth insulation layer by removing a portion of a fifth main insulation layer of the fifth insulation layer which does not overlap the fifth auxiliary insulation layer.

公开(公告)号：US11189677B2

公开(公告)日：2021-11-30

申请号：US16539761

申请日：2019-08-13

Applicant: Samsung Display Co., Ltd.

Inventor： Joon Seok Park ,  Yeon Keon Moon ,  Kwang Suk Kim ,  Tae Sang Kim ,  Geunchul Park ,  Kyung Jin Jeon

IPC: H01L27/32 ,  H01L51/56

Abstract: An organic light emitting diode display device includes a substrate, a first oxide transistor, a second oxide transistor, and a sub-pixel structure. The substrate has a display region including a plurality of sub-pixel regions and a peripheral region located in a side of the display region. The first oxide transistor is disposed in the peripheral region on the substrate, and includes a first oxide semiconductor pattern that includes tin (Sn). The second oxide transistor is disposed in the sub-pixel regions each on the substrate, and includes a second oxide semiconductor pattern. The sub-pixel structure is disposed on the second oxide transistor.

公开(公告)号：US09553201B2

公开(公告)日：2017-01-24

申请号：US14179452

申请日：2014-02-12

Applicant: Samsung Display Co., Ltd. ,  Kobe Steel, Ltd.

Inventor： Byung Du Ahn ,  Ji Hun Lim ,  Gun Hee Kim ,  Kyoung Won Lee ,  Je Hun Lee ,  Hiroshi Goto ,  Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Yeon Hong Kim ,  Yeon Gon Mo ,  Kwang Suk Kim

IPC: H01L27/14 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

Abstract translation: 本发明构思涉及薄膜晶体管和薄膜晶体管阵列面板，并且详细地涉及包括氧化物半导体的薄膜晶体管。 根据本发明构思的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 第一半导体和第二半导体，其与栅电极重叠，栅极绝缘层插入其间，第一半导体和第二半导体彼此接触; 连接到所述第二半导体的源电极; 和连接到第二半导体并面向源电极的漏电极，其中第二半导体包括不包括在第一半导体中的镓（Ga），并且第二半导体中的镓（Ga）的含量大于0 。 ％且小于或等于约33at。 ％。

公开(公告)号：US10916196B2

公开(公告)日：2021-02-09

申请号：US16550966

申请日：2019-08-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yeon Keon Moon ,  Joon Seok Park ,  Kwang Suk Kim ,  Tae Sang Kim ,  Geunchul Park ,  Jun Hyung Lim ,  Kyungjin Jeon

IPC: G09G3/3258 ,  G09G3/3291

Abstract: An organic light emitting display device may include a display panel, a source driving circuit, and a voltage generator. The display panel may include a pixel circuit including a driving transistor to drive an organic light emitting diode. The driving transistor may have four independent terminals including first and second gate electrodes. The source driving circuit may provide a data voltage to the pixel circuit. The voltage generator may apply an independent bias voltage to the second gate electrode of the driving transistor to control a driving voltage range of the driving transistor.

公开(公告)号：US10438976B2

公开(公告)日：2019-10-08

申请号：US16243702

申请日：2019-01-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Jin Cho ,  Joon-Hwa Bae ,  Byoung Kwon Choo ,  Byung Hoon Kang ,  Kwang Suk Kim ,  Woo Jin Cho ,  Jun Hyuk Cheon

IPC: H01L27/12 ,  H01L21/3105 ,  G09G3/3233 ,  C09G1/02 ,  B24B31/00 ,  H01L27/32 ,  H01L21/02 ,  H01L29/786 ,  H01L21/66

Abstract: A method for manufacturing a display device includes forming a first gate metal wire on a substrate, forming a first insulation layer that covers the first gate metal wire, forming a second gate metal wire on the first insulation layer, forming a second main insulation layer that covers the second gate metal wire, forming a second auxiliary insulation layer on the second main insulation layer, forming an exposed portion of an upper surface of the second main insulation layer by polishing the second auxiliary insulation layer, and forming a first data metal wire on the second main insulation layer and the second auxiliary insulation layer.