公开(公告)号：US20170148397A1

公开(公告)日：2017-05-25

申请号：US15179080

申请日：2016-06-10

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： WOONYONG LIM ,  KYEONGSEOK LEE ,  JAEHYUN KOH ,  SUNG-JUN KIM ,  JEONG-HYUN KIM ,  SUNGSOO CHOI

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3685 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0242

Abstract: A display apparatus includes a display panel, a timing controller and a data driver. The display panel includes a data line and first and second pixels connected to the data line. The timing controller generates a data signal and a data kickback control signal in response to input image data. The data driver generates first and second data voltages in response to the data signal, generates a data kickback signal in response to the data kickback control signal, processes the data voltages and the data kickback signal, and outputs the first data voltage to the data line during a first duration, the second data voltage to the data line during a second duration, and a first kickback data voltage to the data line during a first data kickback duration. The first data kickback duration is between the first and second durations.

公开(公告)号：US20220148531A1

公开(公告)日：2022-05-12

申请号：US17387235

申请日：2021-07-28

Applicant: Samsung Display Co., Ltd.

Inventor： GWANGSOO AHN ,  JONG JAE LEE ,  SUNGSOO CHOI

IPC: G09G3/36

Abstract: A display device includes a display panel including a gate line, a data line, a gate driver outputting a gate signal to the gate line, a data driver outputting a data voltage to the data line and a power voltage generator. The power voltage generator generates a gate-on voltage, a gate-off voltage, and a gate clock signal toggled between the gate-on voltage and the gate-off voltage, detects a current level of a gate clock current, cuts off power of the display device when a count of the gate clock current higher than or equal to a first current level is greater than or equal to a reference count, and cuts off the power of the display device when the gate clock current is higher than or equal to a second current level higher than the first current level in an initial frame after the display device is turned on.