公开(公告)号：US09570624B2

公开(公告)日：2017-02-14

申请号：US14620907

申请日：2015-02-12

Applicant: Samsung Display Co., Ltd.

Inventor： Woong-Hee Jeong ,  Sun-Kwang Kim ,  Hyeon-Sik Kim ,  Byung-Du Ahn ,  Chaun-Gi Choi

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, an oxide buffer layer, a protective layer, and source and drain electrodes. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate. The oxide semiconductor layer is formed on the gate insulating layer and includes a source, a channel and a drain region. The oxide buffer layer is formed on the oxide semiconductor layer, and has a carrier concentration lower than that of the oxide semiconductor layer. The protective layer is formed on the oxide buffer layer and the gate insulating layer, and has contact holes formed therein so that the oxide buffer layer in the source and drain regions are exposed therethrough. The source and drain electrodes are coupled with the oxide buffer layer in the source and drain regions through the contact holes.

Abstract translation: 薄膜晶体管包括栅电极，栅极绝缘层，氧化物半导体层，氧化物缓冲层，保护层以及源极和漏极。 栅电极形成在基板上。 栅极绝缘层形成在基板上。 氧化物半导体层形成在栅极绝缘层上并且包括源极，沟道和漏极区。 氧化物缓冲层形成在氧化物半导体层上，其载流子浓度低于氧化物半导体层的载流子浓度。 保护层形成在氧化物缓冲层和栅极绝缘层上，并且在其中形成有接触孔，使得源极和漏极区域中的氧化物缓冲层暴露在其中。 源电极和漏电极通过接触孔与源区和漏区中的氧化物缓冲层耦合。

公开(公告)号：US20150144952A1

公开(公告)日：2015-05-28

申请号：US14521274

申请日：2014-10-22

Applicant: Samsung Display Co., Ltd.

Inventor： Sun-Kwang Kim ,  Chaun-Gi Choi ,  Dong-Han Kang ,  Jae-Sik Kim ,  Hyeon-Sik Kim ,  Woong-Hee Jeong

IPC: H01L27/32 ,  H01L29/45 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/3262 ,  H01L27/124 ,  H01L27/3276 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A display substrate, method of manufacturing the same, and a display device including the same are disclosed. In one aspect, a display substrate includes a first gate electrode formed on a base substrate, a scan line electrically connected to the first gate electrode, a gate insulation layer, an etch stop layer and a passivation layer formed on the base substrate to at least partially overlap the first gate electrode and the scan line, and a data line formed on the passivation layer to at least partially overlap the scan line.

Abstract translation: 公开了一种显示基板及其制造方法及包括该显示基板的显示装置。 在一个方面，一种显示基板包括形成在基底基板上的第一栅极电极，至少与第一栅电极电连接的扫描线，栅绝缘层，蚀刻停止层和形成在基底基板上的钝化层 部分地与第一栅电极和扫描线重叠，以及形成在钝化层上以与扫描线至少部分重叠的数据线。

公开(公告)号：US09921794B2

公开(公告)日：2018-03-20

申请号：US15015159

申请日：2016-02-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jong-Chan Lee ,  So-Young Koo ,  Myoung-Geun Cha ,  Yoon-Ho Khang ,  Myoung-Hwa Kim ,  Woong-Hee Jeong

IPC: G06F3/14 ,  G09G3/20

CPC classification number: G06F3/1446 ,  G09G3/20 ,  G09G2300/026 ,  G09G2310/0232 ,  G09G2320/0233

Abstract: A blind display device includes a plurality of curved display panels, a support, and a plurality of rotators. Each of the curved display panels includes a curved display area between a flat display area and a bezel area. The support guides movement of the curved display panels. The rotators couple corresponding ones of the curved display panels to the support and rotate corresponding ones of the curved display panels.

公开(公告)号：US20150243793A1

公开(公告)日：2015-08-27

申请号：US14620907

申请日：2015-02-12

Applicant: Samsung Display Co., Ltd.

Inventor： Woong-Hee Jeong ,  Sun-Kwang Kim ,  Hyeon-Sik Kim ,  Byung-Du Ahn ,  Chaun-Gi Choi

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, an oxide buffer layer, a protective layer, and source and drain electrodes. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate. The oxide semiconductor layer is formed on the gate insulating layer and includes a source, a channel and a drain region. The oxide buffer layer is formed on the oxide semiconductor layer, and has a carrier concentration lower than that of the oxide semiconductor layer. The protective layer is formed on the oxide buffer layer and the gate insulating layer, and has contact holes formed therein so that the oxide buffer layer in the source and drain regions are exposed therethrough. The source and drain electrodes are coupled with the oxide buffer layer in the source and drain regions through the contact holes.

Abstract translation: 薄膜晶体管包括栅电极，栅极绝缘层，氧化物半导体层，氧化物缓冲层，保护层以及源极和漏极。 栅电极形成在基板上。 栅极绝缘层形成在基板上。 氧化物半导体层形成在栅极绝缘层上并且包括源极，沟道和漏极区。 氧化物缓冲层形成在氧化物半导体层上，其载流子浓度低于氧化物半导体层的载流子浓度。 保护层形成在氧化物缓冲层和栅极绝缘层上，并且在其中形成有接触孔，使得源极和漏极区域中的氧化物缓冲层暴露在其中。 源电极和漏电极通过接触孔与源区和漏区中的氧化物缓冲层耦合。