公开(公告)号：US09852674B2

公开(公告)日：2017-12-26

申请号：US14952590

申请日：2015-11-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young Wan Seo ,  Jong Hee Kim ,  Ji Sun Kim ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G3/36 ,  G09G3/20 ,  H02M3/07

CPC classification number: G09G3/20 ,  G09G2310/0264 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  H02M3/073

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

公开(公告)号：US20160293131A1

公开(公告)日：2016-10-06

申请号：US15084022

申请日：2016-03-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jong Hee Kim ,  Ji Sun Kim ,  Young Wan Seo ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G5/00 ,  H03K17/687

CPC classification number: G09G5/00 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

Abstract translation: 栅极驱动器包括从外部输出时钟信号作为门信号的多个级电路。 第j级电路包括：输入单元，用于当第一输入信号被输入到第一输入端时以初始电压对第一节点充电，当初始电压输入时，将时钟信号作为门信号输出到输出端; 提供给第一节点的保持单元，当将时钟信号提供给保持单元时，保持单元将第一节点维持在复位电源电平;以及逆变器单元，用于将时钟信号或复位电源提供给保持单元 。 当第三输入信号被输入到第三输入端时，输入单元将第一节点保持在第二输入信号输入电压到第二输入端。

公开(公告)号：US20160291368A1

公开(公告)日：2016-10-06

申请号：US14997817

申请日：2016-01-18

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Sun Kim ,  Jong Hee Kim ,  Young Wan Seo ,  Jae Keun Lim

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/12

CPC classification number: G02F1/136286 ,  G02F1/1343 ,  H01L27/124 ,  H01L27/1255

Abstract: Embodiments relate to a display device including: a first base substrate; gate lines disposed on the first base substrate, the gate lines extending in a first direction; parasitic capacitance electrodes coupled to the gate lines; data lines extending in a second direction crossing the first direction; transistors, each coupled to one of the gate lines and coupled to one of the data lines; and pixels sequentially arranged in the first direction, each of the pixels coupled to a corresponding one of the transistors, respectively. Each of the transistors includes a gate electrode, a source electrode, and a drain electrode, and at least two drain electrodes among the drain electrodes of the transistors each overlap a corresponding one of the parasitic capacitance electrodes in different areas as viewed from a plan view.

Abstract translation: 实施例涉及一种显示装置，包括：第一基底; 设置在第一基底基板上的栅极线，栅极线沿第一方向延伸; 耦合到栅极线的寄生电容电极; 数据线沿与第一方向交叉的第二方向延伸; 晶体管，每个耦合到一条栅极线并耦合到数据线之一; 以及沿第一方向依次布置的像素，每个像素分别耦合到相应的一个晶体管。 每个晶体管包括栅电极，源电极和漏电极，并且晶体管的漏电极中的至少两个漏极电极与从平面图观察的不同区域中的相应的一个寄生电容电极重叠 。

公开(公告)号：US12216866B2

公开(公告)日：2025-02-04

申请号：US18301974

申请日：2023-04-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji Sun Kim ,  Mu Kyung Jeon

IPC: G06F3/044 ,  G06F3/041 ,  G06V10/147 ,  G06V40/13

Abstract: A fingerprint sensor includes a sensor pixel arranged in a sensing area, including a pixel electrode coupled to a first node; a first transistor coupled between the first node and a first or second power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode; a first capacitor coupled between the first node and a second scan line; a second transistor coupled between a readout line and the first power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode; and a third transistor coupled between the second transistor and the first power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode.

公开(公告)号：US11462178B2

公开(公告)日：2022-10-04

申请号：US17135806

申请日：2020-12-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jang Mi Kang ,  Ji Sun Kim ,  Mu Kyung Jeon

IPC: G09G3/20 ,  G09G3/3283 ,  G09G3/3291 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/3258 ,  H01L27/12 ,  H01L27/32

Abstract: A display device including a light-emitting diode, a first transistor configured to supply a driving current to the light-emitting diode, a second transistor configured to transmit a data signal to the first transistor, a third transistor configured to transmit the data signal compensated with a threshold voltage to a gate electrode of the first transistor, a first scan line connected to a gate electrode of the second transistor, a second scan line connected to a gate electrode of the third transistor and insulated from the first scan line, and a conductive pattern connected to the gate electrode of the first transistor and insulated from the first scan line and the second scan line. The conductive pattern overlaps the first scan line and the second scan line, and the conductive pattern includes a stem part extending in one direction and a branch part branching from the stem part and overlapping the first scan line.

公开(公告)号：US10078995B2

公开(公告)日：2018-09-18

申请号：US15084022

申请日：2016-03-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jong Hee Kim ,  Ji Sun Kim ,  Young Wan Seo ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G5/00 ,  H03K17/687 ,  G09G3/3266 ,  G09G3/36

CPC classification number: G09G5/00 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

公开(公告)号：US11631271B2

公开(公告)日：2023-04-18

申请号：US16162050

申请日：2018-10-16

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Sun Kim ,  Mu Kyung Jeon

IPC: G06V40/13 ,  G06F3/041 ,  G06F3/044 ,  G06V10/147

Abstract: A fingerprint sensor includes a sensor pixel arranged in a sensing area, including a pixel electrode coupled to a first node; a first transistor coupled between the first node and a first or second power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode; a first capacitor coupled between the first node and a second scan line; a second transistor coupled between a readout line and the first power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode; and a third transistor coupled between the second transistor and the first power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode.

公开(公告)号：US10365778B2

公开(公告)日：2019-07-30

申请号：US15942958

申请日：2018-04-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji Sun Kim ,  Jang Mi Kang ,  Il Gon Kim

IPC: G06F3/044 ,  H01L27/32 ,  G06F3/041

Abstract: A display device includes a substrate including a pixel area, and a peripheral area enclosing at least one side of the pixel area, a plurality of pixels provided in the pixel area, each of the plurality of pixels including a light-emitting area from which light is emitted, a light-emitting element which is provided in each of plurality of the pixels and which emits the light, a pixel circuit which is provided in each of the plurality of pixels and which drives the light-emitting element, and a conductive pattern which is disposed between the substrate and the pixel circuit and which overlap the pixel circuit in a plan view. Pixels of the plurality of pixels each may include a sensing unit which is electrically connected to the conductive pattern and which senses a touch of a user.

公开(公告)号：US20160293269A1

公开(公告)日：2016-10-06

申请号：US14970350

申请日：2015-12-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Keun Lim ,  Jong Hee Kim ,  Ji Sun Kim ,  Young Wan Seo ,  Chong Chul Chai

IPC: G11C19/28 ,  G09G5/00

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3674 ,  G09G2300/0871 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/184

Abstract: There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each of the plurality of stages includes a first transistor coupled between a first clock input terminal and an output terminal and having a first gate electrode coupled to a first node, a second transistor coupled between the output terminal and a power input terminal and having a second gate electrode coupled to a second clock input terminal, and a third transistor coupled between the first node and a first input terminal configured to receive the start pulse or an output signal of a previous stage of the stages, the third transistor having a third gate electrode coupled to the second clock input terminal.

Abstract translation: 提供了一种移位寄存器，其包括顺序地耦合到被配置为接收起始脉冲的输入端子的多个级，其中多个级中的每一级包括耦合在第一时钟输入端子和输出端子之间的第一晶体管，并且具有第一 耦合到第一节点的第二晶体管，连接在输出端子和电源输入端子之间并具有耦合到第二时钟输入端子的第二栅极电极的第二晶体管，以及耦合在第一节点和配置的第一输入端子之间的第三晶体管 为了接收所述级的前一级的起始脉冲或输出信号，所述第三晶体管具有耦合到所述第二时钟输入端的第三栅极。

公开(公告)号：US20160293093A1

公开(公告)日：2016-10-06

申请号：US14952590

申请日：2015-11-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young Wan Seo ,  Jong Hee Kim ,  Ji Sun Kim ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0264 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  H02M3/073

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract translation: 解复用器包括：连接在数据输入端和第一输出端之间的第一晶体管; 连接在数据输入端和第二输出端之间的第二晶体管; 以及与所述第一晶体管的栅电极连接的第一预充电电路，所述第一预充电电路包括：并联连接在所述第一晶体管的第一时钟输入端和所述栅电极之间的第三晶体管和第一二极管; 以及连接在第二时钟输入端和第一晶体管的栅电极之间的第一电容器。