公开(公告)号：US20240312914A1

公开(公告)日：2024-09-19

申请号：US18370263

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： JEONGYEON SEO ,  DONG KWON KIM ,  HYONWOOK RA ,  HONGSIK SHIN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/092

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device may include: a substrate comprising an active pattern; a source/drain pattern on the active pattern; a device isolation layer at a lateral side of the active pattern; a lower power structure below a top surface of the substrate; a lower contact penetrating the device isolation layer and connecting the source/drain pattern to the lower power structure; and a power delivery network layer below the top surface of the substrate, wherein the lower power structure comprises a connecting portion connected to the lower contact, and wherein the lower contact comprises a protruding portion buried in the connecting portion.

公开(公告)号：US20230072817A1

公开(公告)日：2023-03-09

申请号：US17849797

申请日：2022-06-27

Applicant: Samsung Electronics Co, Ltd.

Inventor： JUNGHWAN CHUN ,  HONGSIK SHIN ,  KOUNGMIN RYU ,  BONGKWAN BAEK ,  JONGMIN BAEK

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.

公开(公告)号：US20220254928A1

公开(公告)日：2022-08-11

申请号：US17529406

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： HONGSIK SHIN ,  WONHYUK LEE ,  DONGKWON KIM ,  JINWOOK LEE

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088

Abstract: Semiconductor devices may include a substrate, an active region that is on the substrate and extends in a first direction, a gate structure that traverses the active region and extends in a second direction that may be different from the first direction, a source/drain region on the active region adjacent a side of the gate structure, an insulating layer on the substrate, the gate structure and the source/drain region, and a contact structure that is in the insulating layer and is connected to the source/drain region. In the source/drain region, a contact region that is in contact with the contact structure includes first and second side regions spaced apart from each other in the second direction and a central region between the first and second side regions, and at least one of the first and second side regions may include a recess.