IMAGE SENSOR
    1.
    发明申请

    公开(公告)号:US20230044820A1

    公开(公告)日:2023-02-09

    申请号:US17735605

    申请日:2022-05-03

    Abstract: An image sensor includes a substrate having a plurality of pixel regions and a deep device isolation pattern disposed in the substrate between the pixel regions. The pixel regions include first, second, third, and fourth pixel regions, which are adjacent to each other in first and second directions. The deep device isolation pattern includes first portions interposed between the first and second pixel regions and between the third and fourth pixel regions and spaced apart from each other in the second direction, and second portions interposed between the first and third pixel regions and between the second and fourth pixel regions and spaced apart from each other in the first direction. The first pixel region includes a first extended active pattern, which is extended to the second pixel region in the first direction and is disposed between the first portions of the deep device isolation pattern.

    IMAGE SENSOR USING A BOOSTING CAPACITOR AND A NEGATIVE BIAS VOLTAGE

    公开(公告)号:US20210029316A1

    公开(公告)日:2021-01-28

    申请号:US16801887

    申请日:2020-02-26

    Abstract: An image sensor includes a photodiode generating a charge in response to light, a transfer transistor connecting the photodiode and a floating diffusion, a reset transistor connected between the floating diffusion and a power node, a boosting capacitor connected to the floating diffusion, and adjusting a capacity of the floating diffusion in response to a boosting control signal, and a bias circuit having first and second current circuits for supplying different bias currents to an output node to which a voltage signal corresponding to a charge accumulated in the floating diffusion is output. The boosting control signal decreases from a high level to a low level after the transfer transistor is turned off, and the reset transistor is switched from a turned on state to a turned off state when the bias currents of the first and second current circuits are simultaneously provided to the output node.

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