公开(公告)号：US20140331025A1

公开(公告)日：2014-11-06

申请号：US14269560

申请日：2014-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Seok KWON ,  Suk-Jin KIM

IPC: G06F9/38

CPC classification number: G06F9/3889 ,  G06F9/30087 ,  G06F9/30189

Abstract: A reconfigurable processor and an operation method thereof are provided. The reconfigurable processor may include: a controller configured to control operations of a first mode, in which a first portion of a program that does not utilize loop acceleration is processed, and a second mode, in which a second portion for the program that utilizes the loop acceleration is processed, based on whether an instruction to control parallel operations of the first mode and the second mode is executed; and a shared register file configured to transfer data between the first mode and the second mode.

Abstract translation: 提供了一种可重构处理器及其操作方法。 可重构处理器可以包括：控制器，被配置为控制处理第一模式的操作，其中处理不利用循环加速的程序的第一部分和第二模式，其中用于所述程序的第二部分利用 基于是否执行用于控制第一模式和第二模式的并行操作的指令来处理循环加速度; 以及被配置为在第一模式和第二模式之间传送数据的共享寄存器文件。

公开(公告)号：US20140215476A1

公开(公告)日：2014-07-31

申请号：US14160756

申请日：2014-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Woo PARK ,  Suk-Jin KIM

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/3877 ,  G06F15/7867

Abstract: An apparatus and method for sharing a function logic between functional units and a reconfigurable processor are provided. The apparatus for sharing a function logic may include a storage which is configured to store data which is received from two or more functional units in order to share one or more function logics, and an arbitrator which is configured, based on a scheduling rule, to transmit the data stored in the storage into the function logic.

Abstract translation: 提供了一种用于在功能单元和可重构处理器之间共享功能逻辑的装置和方法。 用于共享功能逻辑的装置可以包括：存储器，其被配置为存储从两个或更多个功能单元接收的数据，以便共享一个或多个功能逻辑;以及仲裁器，其基于调度规则被配置为 将存储在存储器中的数据发送到功能逻辑。

公开(公告)号：US20150006850A1

公开(公告)日：2015-01-01

申请号：US14314282

申请日：2014-06-25

Applicant: Samsung Electronics Co., Ltd

Inventor： Ki-Seok KWON ,  Min-Wook AHN ,  Dong-Kwan SUH ,  Suk-Jin KIM

IPC: G06F9/30

CPC classification number: G06F9/3891 ,  G06F9/3828

Abstract: Provided is a processor with a heterogeneous clustered architecture. The processor comprises a first cluster comprising a first functional unit configured to process a first type of instruction, and a register whose I/O ports are connected to I/O ports of the functional unit; and a second cluster comprising a second functional unit configured to process the first type of instruction and second type of instruction, and a second register whose I/O ports are connected to I/O ports of the second functional unit.

Abstract translation: 提供了具有异构群集体系结构的处理器。 所述处理器包括：第一集群，包括被配置为处理第一类型的指令的第一功能单元和其I / O端口连接到所述功能单元的I / O端口的寄存器; 以及第二集群，包括被配置为处理所述第一类型的指令和第二类型的指令的第二功能单元，以及其I / O端口连接到所述第二功能单元的I / O端口的第二寄存器。

公开(公告)号：US20140214913A1

公开(公告)日：2014-07-31

申请号：US14166076

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeong-Seok YU ,  Suk-Jin KIM

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/503 ,  G06F7/507 ,  G06F2207/382 ,  G06F2207/3828

Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.

Abstract translation: 提供了一种用于通过控制进位传播来支持多种数据类型的加法器。 所述加法器包括多个第一加法区域，被配置为接收输入操作数数据，其中所述多个第一加法区域中的每一个包括预定单位数位，以及多个第二加法区域，被配置为接收多条控制数据 关于操作数数据的类型和操作类型，其中所述多个第二相加区域交替地布置在所述多个第一相加区域之间。