公开(公告)号：US20180301564A1

公开(公告)日：2018-10-18

申请号：US15864330

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesoon Duyeon KWON ,  JeongYun LEE ,  A-reum JI ,  Kyungseok MIN ,  GeumJung SEONG

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/78618 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.