公开(公告)号：US20190157147A1

公开(公告)日：2019-05-23

申请号：US16237948

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo MYUNG ,  GeumJung SEONG ,  Jisoo OH ,  JinWook LEE ,  Dohyoung KIM ,  Yong-Ho JEON

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US20180182845A1

公开(公告)日：2018-06-28

申请号：US15662248

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： GeumJung SEONG ,  JeongYun LEE ,  SeungSoo HONG ,  KyungSeok MIN ,  SeungJu PARK ,  Youngmook OH ,  Bora LIM

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

CPC classification number: H01L29/0653 ,  H01L21/764 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0847

Abstract: Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.

公开(公告)号：US20170200802A1

公开(公告)日：2017-07-13

申请号：US15401562

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo MYUNG ,  GeumJung SEONG ,  Jisoo OH ,  JinWook LEE ,  Dohyoung KIM ,  Yong-Ho JEON

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/16 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US20180145082A1

公开(公告)日：2018-05-24

申请号：US15635583

申请日：2017-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo HONG ,  JeongYun LEE ,  GeumJung SEONG ,  HyunHo JUNG ,  Minchan GWAK ,  Kyungseok MIN ,  Youngmook OH ,  Jae-Hoon WOO ,  Bora LIM

IPC: H01L27/11 ,  H01L29/06

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US20180061958A1

公开(公告)日：2018-03-01

申请号：US15794107

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo MYUNG ,  GeumJung SEONG ,  Jisoo OH ,  JinWook LEE ,  Dohyoung KIM ,  Yong-Ho JEON

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US20180301564A1

公开(公告)日：2018-10-18

申请号：US15864330

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesoon Duyeon KWON ,  JeongYun LEE ,  A-reum JI ,  Kyungseok MIN ,  GeumJung SEONG

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/78618 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.

公开(公告)号：US20150162247A1

公开(公告)日：2015-06-11

申请号：US14531987

申请日：2014-11-03

Applicant: SAMSUNG ELECTRONICS CO., Ltd.

Inventor： Yong-Joon CHOI ,  MYEONGCHEOL KIM ,  CHEOL KIM ,  GeumJung SEONG ,  Hak-Sun LEE ,  Haegeon JUNG ,  Ji-Eun HAN

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/0886

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract translation: 本公开提供半导体器件及其制造方法。 该方法包括使用形成在衬底上的第一掩模图案来蚀刻衬底以形成沟槽，形成填充沟槽的初步器件隔离图案，并且包括具有第一厚度的第一和第二区域，在第一区域上形成第二掩模图案，蚀刻 第二区域的上部和第一掩模图案的一部分被第二掩模图案曝光，以形成具有小于第一厚度的第二厚度的第二区域，去除第一和第二掩模图案，以及蚀刻 所述第一区域的上部和所述第二区域具有第二厚度，以形成限定预备鳍型活性图案的器件隔离图案。 还公开了一种包括半导体器件及其制造方法的电子器件。