公开(公告)号：US20180190772A1

公开(公告)日：2018-07-05

申请号：US15862308

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok MIN ,  Sung Dae Suk ,  JeongYun Lee

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: A semiconductor device includes a device isolation layer on a substrate, a first active pattern defined by the device isolation layer, and source/drain regions. The first active pattern extends in a first direction and includes a channel region between a pair of recesses formed at an upper portion of the first active pattern. The source/drain regions fill the pair of recesses in the first active pattern. Each of the source/drain regions include a first semiconductor pattern in the recess and a second semiconductor pattern on the first semiconductor pattern. The source/drain region have an upper portion whose width is less than a width of its lower portion. The second semiconductor pattern has an upper portion whose width is less than a width of its lower portion. The upper portion of the second semiconductor pattern is positioned higher than a top surface of the channel region.

公开(公告)号：US20170236921A1

公开(公告)日：2017-08-17

申请号：US15390754

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungseok MIN ,  Seongjin NAM ,  Sughyun SUNG ,  Youngmook OH ,  Migyeong GWON ,  Hyungdong KIM ,  InWon PARK ,  Hyunggoo LEE

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L21/683 ,  H01L29/161 ,  H01L29/165 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/6833 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

公开(公告)号：US20180145082A1

公开(公告)日：2018-05-24

申请号：US15635583

申请日：2017-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo HONG ,  JeongYun LEE ,  GeumJung SEONG ,  HyunHo JUNG ,  Minchan GWAK ,  Kyungseok MIN ,  Youngmook OH ,  Jae-Hoon WOO ,  Bora LIM

IPC: H01L27/11 ,  H01L29/06

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US20180301564A1

公开(公告)日：2018-10-18

申请号：US15864330

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesoon Duyeon KWON ,  JeongYun LEE ,  A-reum JI ,  Kyungseok MIN ,  GeumJung SEONG

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/78618 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.

公开(公告)号：US20170133263A1

公开(公告)日：2017-05-11

申请号：US15342456

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok MIN ,  Moojin KIM ,  Seongjin NAM ,  Sughyun SUNG ,  YoungHoon SONG ,  Youngmook OH

IPC: H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01J2237/3347 ,  H01L21/02118 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/10879

Abstract: A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.