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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210119617A1

    公开(公告)日：2021-04-22

    申请号：US16866941

    申请日：2020-05-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun LEE ,  Min Su KIM ,  Ah Reum KIM

    IPC: H03K3/3562 ,  H01L23/528 ,  H01L27/02

    Abstract: A semiconductor device is provided. The semiconductor device includes a clock gate line supplying a clock signal, an inverted clock gate line disposed in parallel to the clock gate line and supplying an inverted clock signal, a first latch circuit performing a first latch operation based on the clock signal and the inverted clock signal and a second latch circuit disposed on a side of the first latch circuit in a first direction, receiving an output of the first latch circuit, and operating based on the clock signal and the inverted clock, wherein the clock gate line and the inverted clock gate line extend in the first direction and are shared by the first and second latch circuits.

    CLOCK GATING CIRCUIT
    2.
    发明申请
    CLOCK GATING CIRCUIT 审中-公开

    公开(公告)号：US20190173472A1

    公开(公告)日：2019-06-06

    申请号：US16259631

    申请日：2019-01-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ah-Reum KIM ,  Hyun LEE ,  Min-su KIM

    IPC: H03K19/0185 ,  H03K3/356 ,  H03K3/037 ,  H03K19/00 ,  H03K3/012

    CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

    MONITORING APPARATUS AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME
    3.
    发明申请
    MONITORING APPARATUS AND SEMICONDUCTOR MANUFACTURING APPARATUS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190139796A1

    公开(公告)日：2019-05-09

    申请号：US15956192

    申请日：2018-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-kil LEE ,  Sung-yoon RYU ,  Hyun LEE ,  Yu-sin YANG ,  Q-han PARK

    IPC: H01L21/67 ,  H01L21/66

    Abstract: An apparatus for manufacturing a semiconductor device is provided. The apparatus for manufacturing a semiconductor device may include a mass flow controller configured to control a flow of a process gas supplied to a process chamber, the mass flow controller configured to adjust an outflow rate of the process gas exiting the mass flow controller in response to a correction signal, the correction signal generated based on a difference between an inflow rate of the process gas flowing into the mass flow controller and a reference flow rate, a sensor configured to measure a chamber pressure inside the process chamber, an exhaust valve configured to adjust an exhaust speed of an exhaust gas exhausted from the process chamber; and a monitoring apparatus configured to detect a defect of the mass flow controller based on the correction signal, the chamber pressure, and the exhaust speed of the exhaust valve.

    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF
    4.
    发明申请
    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230084175A1

    公开(公告)日：2023-03-16

    申请号：US17983929

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongwoo KIM ,  Minsu KIM ,  Yonggeol KIM ,  Hyun LEE ,  Hyunchul HWANG

    IPC: H03K3/037 ,  H03K19/00 ,  H03K3/3562

    Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

    SEMICONDUCTOR CIRCUIT
    6.
    发明申请
    SEMICONDUCTOR CIRCUIT 审中-公开
    半导体电路

    公开(公告)号：US20160315616A1

    公开(公告)日：2016-10-27

    申请号：US15139949

    申请日：2016-04-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ah-Reum KIM ,  Hyun LEE ,  Min-Su KIM

    IPC: H03K19/0185 ,  H03K19/00

    CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

    Abstract translation: 提供半导体电路。 半导体电路包括：第一电路，被配置为基于时钟信号的电压电平将第一节点的值传播到第二节点; 第二电路，被配置为基于所述时钟信号的电压电平将所述第二节点的值传播到第三节点; 以及第三电路，被配置为基于所述第二节点的电压电平和所述时钟信号的电压电平来确定所述第三节点的值，其中所述第一电路包括门控到所述第一节点的电压电平的第一晶体管， 第二晶体管，其与第一晶体管串联连接，并与第三晶体管的电压电平相连，第三晶体管与第一和第二晶体管并联连接，并且选通到时钟信号的电压电平，以提供第一晶体管的值 节点到第二个节点。

    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF
    8.
    发明申请
    FLIP-FLOP, MASTER-SLAVE FLIP-FLOP, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210152161A1

    公开(公告)日：2021-05-20

    申请号：US16930658

    申请日：2020-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongwoo KIM ,  Minsu KIM ,  Yonggeol KIM ,  Hyun LEE ,  Hyunchul HWANG

    IPC: H03K3/037 ,  H03K19/00

    Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

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