公开(公告)号：US20230246017A1

公开(公告)日：2023-08-03

申请号：US18192712

申请日：2023-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGOK LEE ,  SANGDO PARK ,  JUN SEOMUN ,  BONGHYUN LEE

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.

公开(公告)号：US20210174001A1

公开(公告)日：2021-06-10

申请号：US17022233

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  BONGHYUN LEE

IPC: G06F30/3953 ,  G06F30/392 ,  G06F30/398 ,  G03F1/36

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20220215153A1

公开(公告)日：2022-07-07

申请号：US17702879

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  BONGHYUN LEE

IPC: G06F30/3953 ,  G03F1/36 ,  G06F30/398 ,  G06F30/392

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20210104508A1

公开(公告)日：2021-04-08

申请号：US16946620

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGOK LEE ,  SANGDO PARK ,  JUN SEOMUN ,  BONGHYUN LEE

IPC: H01L27/02

Abstract: Semiconductor devices may include standard cells arranged in a first direction and a second direction intersecting the first direction. Both the first and second directions may be parallel to an upper surface of the substrate. Each of the standard cells may include semiconductor elements. The semiconductor device may also include filler cells between two standard cells, and each of the filler cells may include a filler active region and a filler contact connected to the filler active region and may extend in the first direction. The semiconductor device may further include a lower wiring pattern electrically connected to at least one of the semiconductor elements and may extend into at least one of the filler cells in the second direction, and the filler contacts may include wiring filler contacts lower than the lower wiring pattern and connected to at least one of the lower wiring pattern.