公开(公告)号：US20210174001A1

公开(公告)日：2021-06-10

申请号：US17022233

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  BONGHYUN LEE

IPC: G06F30/3953 ,  G06F30/392 ,  G06F30/398 ,  G03F1/36

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20240265188A1

公开(公告)日：2024-08-08

申请号：US18641386

申请日：2024-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  Bonghyun Lee

IPC: G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/3953 ,  G03F1/36 ,  G06F30/392 ,  G06F30/398

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

公开(公告)号：US20220215153A1

公开(公告)日：2022-07-07

申请号：US17702879

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGDEOK KIM ,  MUNJUN SEO ,  BONGHYUN LEE

IPC: G06F30/3953 ,  G03F1/36 ,  G06F30/398 ,  G06F30/392

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.