公开(公告)号：US20160379985A1

公开(公告)日：2016-12-29

申请号：US15191552

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Seok CHOI ,  Young-min KO ,  HONGGUN KIM ,  JONGMYEONG LEE ,  BYOUNGDEOG CHOI

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/311

CPC classification number: H01L28/90 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852

Abstract: A method for manufacturing a semiconductor device includes forming a storage node hole passing through an upper support layer, a bowing prevention layer and an upper mold layer using a dry etching process, forming a lower electrode in the storage node hole, patterning the upper support layer and the bowing prevention layer to expose a portion of the upper mold layer, removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process, and sequentially forming a dielectric layer and an upper electrode that cover the lower electrode. An etch rate of the bowing prevention layer may be substantially equal to an etch rate of the upper support layer during the dry etching process. An etch rate of the bowing prevention layer may be higher than an etch rate of the upper support layer during the first wet etching process.

Abstract translation: 一种半导体装置的制造方法，其特征在于，包括：通过干式蚀刻工序形成穿过上支撑层，弓形防止层和上模层的存储节点孔，在所述存储节点孔中形成下电极，使所述上支撑层 以及所述弯曲防止层，以暴露所述上模层的一部分，使用第一湿蚀刻工艺去除所述上模层和所述防弓层的至少一部分，并且顺序地形成覆盖所述上模具层的电介质层和上电极 下电极。 弯曲防止层的蚀刻速率可以基本上等于在干蚀刻工艺期间上支撑层的蚀刻速率。 在第一湿法蚀刻工艺期间，防弓层的蚀刻速率可高于上支撑层的蚀刻速率。