公开(公告)号：US20230079697A1

公开(公告)日：2023-03-16

申请号：US17868401

申请日：2022-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO LEE ,  YUNSE OH ,  BYUNG-SUNG KIM ,  SUTAE KIM ,  Seung CHOI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed is a semiconductor device including: a substrate including a first active pattern separated into a pair of first active patterns by a trench; a device isolation layer filling the trench; first source/drain patterns on the first active pattern; a first channel pattern connected to the first source/drain patterns and including semiconductor patterns; a first dummy gate electrode that extends while being adjacent to a first sidewall of the trench; a gate electrode that is spaced apart in the first direction from the first dummy gate electrode and extends while running across the first channel pattern, a gate capping pattern on the gate electrode; a gate contact coupled to the gate electrode; and a separation pattern extending between the gate electrode and the first dummy gate electrode. A top surface of the separation pattern is at a same level as that of the gate capping pattern.

公开(公告)号：US20230333160A1

公开(公告)日：2023-10-19

申请号：US18075542

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYUNG-SUNG KIM ,  YUN-HYOK CHOI ,  GYUYEOL KIM ,  SUNGJUNG KIM ,  CHEOL-HEUI PARK ,  SANGHOON LEE ,  JAE-WOONG CHOI

IPC: G01R31/3177 ,  G04F10/00

CPC classification number: G01R31/3177 ,  G04F10/005

Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.