公开(公告)号：US20250142812A1

公开(公告)日：2025-05-01

申请号：US18896219

申请日：2024-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyoun Song ,  Jamin Koo ,  Beomseo Kim ,  Jonghyeok Kim ,  Daeyoung Moon ,  Changwoo Seo ,  Wonseok Yoo ,  Chunhyung Chung

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first active region, a bit line on the substrate to cross the first active region, a bit line contact between the bit line and the first active region and in a bit line contact hole extending into the substrate, a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole, a bit line spacer on a sidewall of the bit line, an anti-oxidation layer between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer, and a buried contact in a buried contact hole, passing through the bit line contact spacer, and contacting the first active region, in which the anti-oxidation layer includes a silicon-containing material including SiOx, where 0

公开(公告)号：US20240049454A1

公开(公告)日：2024-02-08

申请号：US18210796

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomseo Kim ,  Jamin Koo

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/02

Abstract: A semiconductor device includes an active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to the upper surface of the substrate, an isolation pattern covering a sidewall of the active pattern, an epitaxial layer on the active pattern and including single crystalline silicon doped with impurities, an impurity region in a portion of the active pattern under the epitaxial layer and including impurities, a conductive filling pattern on the epitaxial layer, a spacer structure on a sidewall of the conductive filling pattern, and a bit line structure on the conductive filling pattern.

公开(公告)号：US20240389303A1

公开(公告)日：2024-11-21

申请号：US18663449

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Beomseo Kim

IPC: H10B12/00

Abstract: A semiconductor device includes an active region disposed in a substrate, a device isolation layer defining the active region, a gate structure disposed in the substrate and extending in a first horizontal direction to cross the active region, bit line structures crossing the gate structure and extending in a second horizontal direction, intersecting the first horizontal direction, and a contact plug between the bit line structures. The active region includes a first source/drain region, a second source/drain region, and a channel region. The first and second source/drain regions are spaced apart from each other by the gate structure. The first source/drain region includes a first lower region and a first upper region on the first lower region. The first lower region is a first crystal region, and the first upper region is a second crystal region, different from the first crystal region. The contact plug contacts the first upper region.