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    Semiconductor memory device and a method of manufacturing the same
    2.
    发明授权
    Semiconductor memory device and a method of manufacturing the same 有权

    公开(公告)号：US12200922B2

    公开(公告)日：2025-01-14

    申请号：US18116883

    申请日：2023-03-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

    SEMICONDUCTOR DEVICE HAVING SOURCE/DRAIN REGIONS
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SOURCE/DRAIN REGIONS 有权

    公开(公告)号：US20240389303A1

    公开(公告)日：2024-11-21

    申请号：US18663449

    申请日：2024-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daeyoung Moon ,  Jamin Koo ,  Beomseo Kim

    IPC: H10B12/00

    Abstract: A semiconductor device includes an active region disposed in a substrate, a device isolation layer defining the active region, a gate structure disposed in the substrate and extending in a first horizontal direction to cross the active region, bit line structures crossing the gate structure and extending in a second horizontal direction, intersecting the first horizontal direction, and a contact plug between the bit line structures. The active region includes a first source/drain region, a second source/drain region, and a channel region. The first and second source/drain regions are spaced apart from each other by the gate structure. The first source/drain region includes a first lower region and a first upper region on the first lower region. The first lower region is a first crystal region, and the first upper region is a second crystal region, different from the first crystal region. The contact plug contacts the first upper region.

    Semiconductor devices
    5.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11716839B2

    公开(公告)日：2023-08-01

    申请号：US17357139

    申请日：2021-06-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonkyu Rhee ,  Jiyoung Ahn ,  Hyunyong Kim ,  Jamin Koo ,  Yongseok Ahn ,  Minsub Um ,  Sangho Lee ,  Yoonyoung Choi

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/34

    Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

    Semiconductor devices
    6.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11729963B2

    公开(公告)日：2023-08-15

    申请号：US17331725

    申请日：2021-05-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyokyoung Kim ,  Jamin Koo ,  Jonghyeok Kim ,  Daeyoung Moon

    IPC: H01L27/108 ,  H10B12/00 ,  H01L29/423

    CPC classification number: H10B12/30 ,  H01L29/4236

    Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.

    Semiconductor memory device using different crystallinities in storage node contact and a method of manufacturing the same
    7.
    发明授权
    Semiconductor memory device using different crystallinities in storage node contact and a method of manufacturing the same 有权

    公开(公告)号：US11631677B2

    公开(公告)日：2023-04-18

    申请号：US17358055

    申请日：2021-06-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明公开
    INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240105791A1

    公开(公告)日：2024-03-28

    申请号：US18371869

    申请日：2023-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daeyoung MOON ,  Jamin Koo ,  Kyuwan Kim ,  Jonghyeok Kim ,  Hyokyoung Kim ,  Kisoo Park

    IPC: H01L29/423 ,  H10B12/00

    CPC classification number: H01L29/4236 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

    Abstract: An integrated circuit device includes a substrate including a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.

    SEMICONDUCTOR DEVICES
    9.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240049454A1

    公开(公告)日：2024-02-08

    申请号：US18210796

    申请日：2023-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Beomseo Kim ,  Jamin Koo

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/02

    Abstract: A semiconductor device includes an active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to the upper surface of the substrate, an isolation pattern covering a sidewall of the active pattern, an epitaxial layer on the active pattern and including single crystalline silicon doped with impurities, an impurity region in a portion of the active pattern under the epitaxial layer and including impurities, a conductive filling pattern on the epitaxial layer, a spacer structure on a sidewall of the conductive filling pattern, and a bit line structure on the conductive filling pattern.

    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220173107A1

    公开(公告)日：2022-06-02

    申请号：US17358055

    申请日：2021-06-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

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