公开(公告)号：US20200210626A1

公开(公告)日：2020-07-02

申请号：US16283725

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Monika TKACZYK ,  Brian C. GRAYSON ,  Mohamad Basem BARAKAT ,  Eric C. QUINNELL ,  Bradley G. BURGESS

IPC: G06F21/72 ,  H04L9/08 ,  G06F9/38

Abstract: According to one general aspect, an apparatus may include a context-specific encryption key circuit configured to generate a key value, wherein the key value is specific to a context of a set of instructions. The apparatus may include a target address prediction circuit configured to provide a target address for a next instruction in the set of instructions. The apparatus may include a target address memory configured to store an encrypted version of the target address, wherein the target address is encrypted using, at least in part, the key value. The apparatus may further include an instruction fetch circuit configured to decrypt the target address using, at least in part, the key value, and retrieve the target address.

公开(公告)号：US20180165211A1

公开(公告)日：2018-06-14

申请号：US15422442

申请日：2017-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hao WANG ,  Dilip MUTHUKRISHNAN ,  Brian C. GRAYSON

IPC: G06F12/0875 ,  G06F12/0888 ,  G06F12/0897

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0897 ,  G06F2212/202 ,  G06F2212/502

Abstract: According to one general aspect, an apparatus may include a load/store circuit and a region size detection circuit. The load/store circuit may be configured to issue a plurality of store instructions to store data in a memory system. The region size detection circuit may be configured to determine a cache from a plurality of caches to store a stream of store instructions based upon, at least in part, by tracking multiple cache-line address entries in the plurality of store instructions, wherein each address entry is updated at a different frequency.