公开(公告)号：US20240248511A1

公开(公告)日：2024-07-25

申请号：US18476508

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumsoo Lee

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: The present disclosure provides a clock driver, an operating method thereof, a memory device including the clock driver, and a memory system. A clock driver according to an embodiment includes a differential buffer configured to output a differential amplified clock signal pair based on a differential external clock signal pair, and a signal coupler configured to generate a differential internal clock signal pair based on the differential amplified clock signal pair, and output a chip enable signal to the memory chip based on the differential internal clock signal pair.

公开(公告)号：US12273113B2

公开(公告)日：2025-04-08

申请号：US18101653

申请日：2023-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumsoo Lee

IPC: G11C11/4096 ,  H03K3/03 ,  H03K5/13 ,  H03K19/08 ,  H03K5/00

Abstract: A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

公开(公告)号：US20240012443A1

公开(公告)日：2024-01-11

申请号：US18105341

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumsoo Lee

IPC: G06F1/08 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: Disclosed is a register clock driver which includes an operating circuit that buffers a command and an address received from an external memory controller, and a training circuit that performs a first training operation and a second training operation in an initialization operation. In the first training operation, one of a plurality of reference clock signals is selected as a first training clock signal for sampling output signals output from the operating circuit. In the second training operation, a second training clock signal for sampling the output signals is selected through phase adjustment based on the first training clock signal.

公开(公告)号：US11129124B2

公开(公告)日：2021-09-21

申请号：US16449727

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Chaeman Lim ,  Hyejoong Kang ,  Bumsoo Lee

IPC: G01S5/02 ,  H04W64/00

Abstract: An electronic device is provided. The electronic device includes a first wireless communication circuit supporting near-field communication with APs, a second wireless communication circuit supporting cellular communication with base stations, a processor, and a memory. The processor receives a first identifier of a first AP by using the first wireless communication circuit, generates a first determination by confirming whether or not the list includes the first identifier and location information associated with the first identifier, transmits the first identifier to an external server by using the first wireless communication circuit or the second wireless communication circuit at least partially on the basis of the first determination, receives first information regarding a location associated with the first identifier from the external server through the first wireless communication circuit or the second wireless communication circuit, and determines the location of the electronic device at least on the basis of the first information.

公开(公告)号：US11086952B2

公开(公告)日：2021-08-10

申请号：US16510754

申请日：2019-07-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Jinwoo Kim ,  Chaeman Lim ,  Hyejoong Kang ,  Bumsoo Lee

IPC: G06F16/9537 ,  H04W4/029 ,  G06F16/29 ,  G06F16/951 ,  G06F16/2457 ,  G06F16/23 ,  H04W88/08

Abstract: A server device, which includes a communication interface; a memory; and a processor operatively connected to the communication interface and the memory. The memory is configured to store a first database including identifiers of access points and location information. The processor is configured to: receive, from an external electronic device through the communication interface, an identifier of at least one access point including a first access point collected by the external device and an identifier of a base station, identify location information matching the identifier of the at least one access point and/or the identifier of the base station in the first database, and update location information matching an identifier of the first access point in the first database based on the identified location information.