公开(公告)号：US10103163B2

公开(公告)日：2018-10-16

申请号：US15249389

申请日：2016-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jin-I Lee ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/41 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

公开(公告)号：US09716181B2

公开(公告)日：2017-07-25

申请号：US15176611

申请日：2016-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Ouk Nam ,  Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-l Lee ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78672 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1207 ,  H01L29/78642

Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.