公开(公告)号：US10103163B2

公开(公告)日：2018-10-16

申请号：US15249389

申请日：2016-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jin-I Lee ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/41 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

公开(公告)号：US09905568B2

公开(公告)日：2018-02-27

申请号：US15251580

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hoon Son ,  Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Duk Lee ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.