Semiconductor memory device and method of manufacturing the same

    公开(公告)号:US11653493B2

    公开(公告)日:2023-05-16

    申请号:US16874159

    申请日:2020-05-14

    CPC classification number: H01L27/11556 G11C5/025 H01L27/11582

    Abstract: A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.

    Method of manufacturing semiconductor devices
    3.
    发明授权
    Method of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号:US09564343B2

    公开(公告)日:2017-02-07

    申请号:US14990353

    申请日:2016-01-07

    Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.

    Abstract translation: 具有包含氧化物的绝缘层的衬底被加载到腔室中,并且通过将包括蚀刻源气体的处理气体注入到室中来去除绝缘层的至少一部分。 去除处理以多次重复第一周期和第二周期的脉冲类型执行。 蚀刻源气体在第一时段期间以第一流量供应,并且在第二时段期间以小于第一流量的第二流量供应。 在除去过程中,室内温度保持在100℃或更高。

    Method and apparatus for plasma etching

    公开(公告)号:US10096453B2

    公开(公告)日:2018-10-09

    申请号:US15133989

    申请日:2016-04-20

    Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

    PLASMA SENSOR MODULE
    10.
    发明公开

    公开(公告)号:US20240071737A1

    公开(公告)日:2024-02-29

    申请号:US18188540

    申请日:2023-03-23

    CPC classification number: H01J37/32917 G01N9/00 H01J2237/24585

    Abstract: A plasma sensor module may include an upper substrate, a lower substrate, at least one probe and a printed circuit board (PCB). The upper substrate may be configured to be exposed to plasma. The lower substrate may contact a lower surface of the upper substrate. The lower substrate may have a thickness that is thicker than a thickness of the upper substrate. The probe may be in the lower substrate. The PCB may be in the lower substrate. The PCB may be configured to apply an alternating current to the probe to detect a density of the plasma. Thus, the structural strength of the plasma sensor module may have improved structural strength.

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